公开(公告)号：US20140312463A1

公开(公告)日：2014-10-23

申请号：US14319029

申请日：2014-06-30

Applicant: Soitec

Inventor： Chantal Arena

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L21/0254 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02647 ,  H01L21/76254 ,  H01L29/0684 ,  H01L29/2003

Abstract: Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.

Abstract translation: 制造半导体器件或结构的方法包括形成覆盖柔性材料层的半导体材料的结构，随后改变柔顺材料的粘度以使半导体材料结构松弛，并且利用松弛的半导体材料结构作为晶种层形成 连续的松弛半导体材料层。 在一些实施例中，半导体材料层可以包括III-V型半导体材料，例如氮化铟镓。 在这种方法中形成了新的中间结构。 工程衬底包括具有松弛晶格结构的连续的半导体材料层。

公开(公告)号：US20140264408A1

公开(公告)日：2014-09-18

申请号：US14211590

申请日：2014-03-14

Applicant: Soitec

Inventor： Jean-Philippe Debray ,  Chantal Arena ,  Heather McFavilen ,  Ding Ding ,  Li Huang

IPC: H01L33/32 ,  H01L33/00 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02

CPC classification number: H01L33/06 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/04 ,  H01L33/12 ,  H01L33/145 ,  H01L33/16 ,  H01L33/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

公开(公告)号：US08741385B2

公开(公告)日：2014-06-03

申请号：US13751558

申请日：2013-01-28

Applicant: Soitec

Inventor： Chantal Arena ,  Christiaan J. Werkhoven ,  Ronald Thomas Bertram, Jr. ,  Ed Lindow

IPC: C23C16/30

CPC classification number: H01L21/0262 ,  C23C16/303 ,  C23C16/448 ,  C30B25/105

Abstract: The present invention relates to the field of semiconductor processing and provides methods that improve chemical vapor deposition (CVD) of semiconductor materials by promoting more efficient thermalization of precursor gases prior to their reaction. In preferred embodiments, the method provides heat transfer structures and their arrangement within a CVD reactor so as to promote heat transfer to flowing process gases. In certain preferred embodiments applicable to CVD reactors transparent to radiation from heat lamps, the invention provides radiation-absorbent surfaces placed to intercept radiation from the heat lamps and to transfer it to flowing process gases.

Abstract translation: 本发明涉及半导体处理领域，并且提供了通过在其反应之前促进前体气体的更有效的热化来改善半导体材料的化学气相沉积（CVD）的方法。 在优选的实施方案中，该方法提供热传递结构及其在CVD反应器内的布置，以便促进对流动的工艺气体的热传递。 在适用于对来自加热灯的辐射透明的CVD反应器的某些优选实施方案中，本发明提供放射吸收表面，其被放置以拦截来自加热灯的辐射并将其转移到流动的工艺气体。

公开(公告)号：US08642995B2

公开(公告)日：2014-02-04

申请号：US13926030

申请日：2013-06-25

Applicant: Soitec

Inventor： Chantal Arena

IPC: H01L29/06

CPC classification number: H01L33/06 ,  B82Y20/00 ,  H01L31/03048 ,  H01L31/035236 ,  H01L31/1848 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32 ,  Y02E10/544 ,  Y02P70/521

Abstract: Radiation-emitting semiconductor devices include a first base region comprising an n-type III-V semiconductor material, a second base region comprising a p-type III-V semiconductor material, and a multi-quantum well structure disposed between the first base region and the second base region. The multi-quantum well structure includes at least three quantum well regions and at least two barrier regions. An electron hole energy barrier between a third of the quantum well regions and a second of the quantum well regions is less than an electron hole energy barrier between the second of the quantum well regions and a first of the quantum well regions. Methods of forming such devices include sequentially epitaxially depositing layers of such a multi-quantum well structure, and selecting a composition and configuration of the layers such that the electron hole energy barriers vary across the multi-quantum well structure.

Abstract translation: 辐射发射半导体器件包括包括n型III-V族半导体材料的第一基极区域，包括p型III-V族半导体材料的第二基极区域和设置在第一基极区域和第二基极区域之间的多量子阱结构， 第二个基地区。 多量子阱结构包括至少三个量子阱区和至少两个势垒区。 量子阱区域中的第三个量子阱区域和第二量子阱区域之间的电子空穴能势垒小于第二量子阱区域和第一量子阱区域之间的电子空穴能势垒。 形成这种器件的方法包括顺序地外延沉积这种多量子阱结构的层，并且选择这些层的组成和构型使得电子空穴能垒在多量子阱结构上变化。

公开(公告)号：US20130285015A1

公开(公告)日：2013-10-31

申请号：US13926030

申请日：2013-06-25

Applicant: Soitec

Inventor： Chantal Arena

IPC: H01L33/06 ,  H01L31/18 ,  H01L31/0304 ,  H01L33/00

CPC classification number: H01L33/06 ,  B82Y20/00 ,  H01L31/03048 ,  H01L31/035236 ,  H01L31/1848 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32 ,  Y02E10/544 ,  Y02P70/521

Abstract: Radiation-emitting semiconductor devices include a first base region comprising an n-type III-V semiconductor material, a second base region comprising a p-type III-V semiconductor material, and a multi-quantum well structure disposed between the first base region and the second base region. The multi-quantum well structure includes at least three quantum well regions and at least two barrier regions. An electron hole energy barrier between a third of the quantum well regions and a second of the quantum well regions is less than an electron hole energy barrier between the second of the quantum well regions and a first of the quantum well regions. Methods of forming such devices include sequentially epitaxially depositing layers of such a multi-quantum well structure, and selecting a composition and configuration of the layers such that the electron hole energy barriers vary across the multi-quantum well structure.

Abstract translation: 辐射发射半导体器件包括包括n型III-V族半导体材料的第一基极区域，包括p型III-V族半导体材料的第二基极区域和设置在第一基极区域和第二基极区域之间的多量子阱结构， 第二个基地区。 多量子阱结构包括至少三个量子阱区和至少两个势垒区。 量子阱区域中的第三个量子阱区域和第二量子阱区域之间的电子空穴能势垒小于第二量子阱区域和第一量子阱区域之间的电子空穴能势垒。 形成这种器件的方法包括顺序地外延沉积这种多量子阱结构的层，并且选择这些层的组成和构型使得电子空穴能垒在多量子阱结构上变化。

公开(公告)号：US20160276530A1

公开(公告)日：2016-09-22

申请号：US15141472

申请日：2016-04-28

Applicant: Soitec

Inventor： Jean-Philippe Debray ,  Chantal Arena ,  Heather McFavilen

IPC: H01L33/06 ,  H01L33/00 ,  H01L33/32 ,  H01L33/14 ,  H01L33/12

CPC classification number: H01L33/06 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L33/007 ,  H01L33/12 ,  H01L33/145 ,  H01L33/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light-emitting device, such as an LED. Luminary devices include such LEDs.

Abstract translation: 半导体结构包括多层InGaN之间的有源区。 有源区可以至少基本上由InGaN组成。 多层InGaN包括至少一个包含InwGa1-wN的阱层和至少一个包含接近至少一个阱层的InbGa1-bN的势垒层。 在一些实施例中，阱层的InwGa1-wN中的w的值在一些实施例中可以大于或等于约0.10且小于或等于约0.40，并且在InbGa1-bN中的b的值在 至少一个阻挡层可以大于或等于约0.01且小于或等于约0.10。 形成半导体结构的方法包括生长这样的InGaN层以形成诸如LED的发光器件的有源区。 照明装置包括这样的LED。

公开(公告)号：US09368344B2

公开(公告)日：2016-06-14

申请号：US14319029

申请日：2014-06-30

Applicant: Soitec

Inventor： Chantal Arena

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L21/0254 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02647 ,  H01L21/76254 ,  H01L29/0684 ,  H01L29/2003

Abstract: Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.

Abstract translation: 制造半导体器件或结构的方法包括形成覆盖柔性材料层的半导体材料的结构，随后改变柔顺材料的粘度以使半导体材料结构松弛，并且利用松弛的半导体材料结构作为晶种层形成 连续的松弛半导体材料层。 在一些实施例中，半导体材料层可以包括III-V型半导体材料，例如氮化铟镓。 在这种方法中形成了新的中间结构。 工程衬底包括具有松弛晶格结构的连续的半导体材料层。

公开(公告)号：US20160145767A1

公开(公告)日：2016-05-26

申请号：US15013448

申请日：2016-02-02

Applicant: Soitec

Inventor： Ronald Thomas Bertram, JR. ,  Christiaan J. Werkhoven ,  Chantal Arena ,  Ed Lindow

IPC: C30B25/14 ,  H01L21/02 ,  C30B29/40

CPC classification number: C30B25/14 ,  C23C16/303 ,  C23C16/45504 ,  C23C16/4557 ,  C23C16/54 ,  C30B29/40 ,  C30B29/406 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/0262 ,  Y10T137/0402

Abstract: Deposition systems include a reaction chamber, and a substrate support structure disposed at least partially within the reaction chamber. The systems further include at least one gas injection device and at least one vacuum device, which together are used to flow process gases through the reaction chamber. The systems also include at least one access gate through which a workpiece substrate may be loaded into the reaction chamber and unloaded out from the reaction chamber. The at least one access gate is located remote from the gas injection device. Methods of depositing semiconductor material may be performed using such deposition systems. Methods of fabricating such deposition systems may include coupling an access gate to a reaction chamber at a location remote from a gas injection device.

公开(公告)号：US08887650B2

公开(公告)日：2014-11-18

申请号：US13966921

申请日：2013-08-14

Applicant: Soitec

Inventor： Chantal Arena ,  Christiaan Werkhoven

IPC: C30B23/00 ,  C30B28/06 ,  C30B25/14 ,  C23C16/30 ,  C23C16/44 ,  C23C16/48 ,  C23C16/54 ,  C30B29/40 ,  H01L21/02

CPC classification number: C30B25/14 ,  C23C16/303 ,  C23C16/4401 ,  C23C16/4412 ,  C23C16/481 ,  C23C16/54 ,  C30B29/403 ,  H01L21/0254 ,  H01L21/0262 ,  Y10T117/10 ,  Y10T117/1008

Abstract: The present invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. In particular, the invention provides apparatus and methods for limiting deposition/condensation of GaCl3 and reaction by-products on an isolation valve that is used in the system and method for forming a monocrystalline Group III-V semiconductor material by reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber.

Abstract translation: 本发明涉及为生产III-N（氮）化合物半导体晶片而专门用于生产GaN晶片的方法和装置。 具体地说，这些方法涉及基本上防止在化学气相沉积（CVD）反应器内的隔离阀装置上形成不需要的材料。 特别地，本发明提供了用于限制用于系统中的隔离阀上的GaCl 3和反应副产物的沉积/冷凝的装置和方法，以及通过使一定量的气态反应形成单晶III-V族半导体材料的方法 III族前体作为一种反应物，一定量的气态V族组分作为反应室中的另一反应物。

公开(公告)号：US20140264265A1

公开(公告)日：2014-09-18

申请号：US14211403

申请日：2014-03-14

Applicant: Soitec

Inventor： Chantal Arena ,  Jean-Philippe Debray ,  Richard Scott Kern

IPC: H01L33/14 ,  H01L33/06

CPC classification number: H01L33/06 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L33/0062 ,  H01L33/0066 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/08 ,  H01L33/12 ,  H01L33/145 ,  H01L33/18 ,  H01L33/32 ,  H01L33/325 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of fainting semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

Abstract translation: 半导体结构包括多层InGaN之间的有源区。 有源区可以至少基本上由InGaN组成。 多层InGaN包括至少一个包含InwGa1-wN的阱层和至少一个包含接近至少一个阱层的InbGa1-bN的势垒层。 在一些实施例中，阱层的InwGa1-wN中的w的值在一些实施例中可以大于或等于约0.10且小于或等于约0.40，并且在InbGa1-bN中的b的值在 至少一个阻挡层可以大于或等于约0.01且小于或等于约0.10。 降低半导体结构的方法包括生长这样的InGaN层以形成诸如LED的发光器件的有源区。 照明装置包括这样的LED。