公开(公告)号：US11854786B2

公开(公告)日：2023-12-26

申请号：US17344530

申请日：2021-06-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-An Lai ,  Te-Hsin Chiu ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng ,  Chia-Tien Wu

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226

摘要： An integrated circuit includes a plurality of first layer deep lines and a plurality of first layer shallow lines. The integrated circuit also includes a plurality of second layer deep lines and a plurality of second layer shallow lines. Each of the first layer deep lines and the first layer shallow lines is in a first conductive layer. Each of the second layer deep lines and the second layer shallow lines is in a second conductive layer above the first conductive layer.

公开(公告)号：US11646314B2

公开(公告)日：2023-05-09

申请号：US17232293

申请日：2021-04-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Meng-Hung Shen ,  Jiann-Tyng Tzeng

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L27/0924 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

摘要： In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess. In some embodiments, the method further includes partially exposing the semiconductor region in a second recess in the first dielectric material and selectively depositing the second dielectric material on the first dielectric material, but not the semiconductor region, in the second recess.

公开(公告)号：US20230064223A1

公开(公告)日：2023-03-02

申请号：US17459697

申请日：2021-08-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L21/768

摘要： An integrated circuit structure is disclosed, including a gate, a first conductive line and a pair of second conductive lines, and a first feed-through via. The gate is disposed on a front side of the integrated circuit structure and extends in a first direction on a first side of a dielectric layer. The first conductive line and a pair of second conductive lines are disposed on a second side, opposite of the first side, of the dielectric layer and on a back side, opposite of the front side, of the integrated circuit structure. The first conductive line is interposed between the pair of second conductive lines in a layout view. The first feed-through via extends through the dielectric layer in a second direction different from the first direction. The first feed-through via couples the gate to the first conductive line.

公开(公告)号：US11374005B2

公开(公告)日：2022-06-28

申请号：US17075578

申请日：2020-10-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Shih-Wei Peng ,  Te-Hsin Chiu ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L21/02 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

摘要： A semiconductor device includes a first transistor of a first conductivity type and a second transistor of a second conductivity type. The first transistor is arranged in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device also includes a first conductive line arranged in a third layer between the first layer and the second layer and extending in the second direction, wherein the first conductive line is configured to electrically connect a first source/drain region of the first active region to a second source/drain region of the second active region.

公开(公告)号：US20240347579A1

公开(公告)日：2024-10-17

申请号：US18757744

申请日：2024-06-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu ,  Te-An Chen

IPC分类号： H01G4/30 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/08

CPC分类号： H01L28/40 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0811

摘要： A semiconductor device and a manufacturing method thereof are provided. The method includes forming an isolation structure in a substrate to define an isolating region and forming a capacitor structure on an upper surface of the isolation structure and comprising a first semiconductor structure and a second semiconductor structure separated by an insulator pattern. The first semiconductor structure and the second semiconductor structure are formed with upper surfaces aligned with one another.

公开(公告)号：US20240332303A1

公开(公告)日：2024-10-03

申请号：US18735302

申请日：2024-06-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Meng-Hung Shen ,  Jiann-Tyng Tzeng

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

摘要： In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess. In some embodiments, the method further includes partially exposing the semiconductor region in a second recess in the first dielectric material and selectively depositing the second dielectric material on the first dielectric material, but not the semiconductor region, in the second recess

公开(公告)号：US12087809B2

公开(公告)日：2024-09-10

申请号：US18078418

申请日：2022-12-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu ,  Te-An Chen

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/768 ,  H01L23/64 ,  H01L27/06 ,  H01L27/08 ,  H01L29/92 ,  H01L49/02

CPC分类号： H01L28/40 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0811

摘要： A semiconductor device and a manufacturing method thereof are provided. The method includes forming an isolation structure in a substrate to define an isolating region and forming a capacitor structure on an upper surface of the isolation structure and comprising a first semiconductor structure and a second semiconductor structure separated by an insulator pattern. The first semiconductor structure and the second semiconductor structure are formed with upper surfaces aligned with one another.

公开(公告)号：US11950413B2

公开(公告)日：2024-04-02

申请号：US18079971

申请日：2022-12-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu

IPC分类号： H01L29/66 ,  H01L21/265 ,  H01L21/28 ,  H01L21/321 ,  H01L21/3213 ,  H01L27/02 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H10B41/40

CPC分类号： H10B41/40 ,  H01L21/26513 ,  H01L21/28052 ,  H01L21/3212 ,  H01L21/32139 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575

摘要： An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm2. Polysilicon gates with these adaptations may be operative with gate voltages of 10 V or higher and may be used in embedded memory devices.

公开(公告)号：US11943921B2

公开(公告)日：2024-03-26

申请号：US17874416

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC分类号： H10B41/44 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30 ,  H10B41/35 ,  H10B41/41 ,  H10B41/42 ,  H10B43/40

CPC分类号： H10B41/44 ,  H01L21/0276 ,  H01L21/28035 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/76802 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/30

摘要： Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. Each memory cell structure of the plurality of memory cell structures comprises a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with a sidewall surface of the select gate electrode within the memory region. A lower inter-layer dielectric layer is disposed on the CESL between the plurality of memory cell structures within the memory region.

公开(公告)号：US11810959B2

公开(公告)日：2023-11-07

申请号：US17829542

申请日：2022-06-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC分类号： H01L29/00 ,  H01L29/423 ,  H01L21/28 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/42376 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/4238 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/665

摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate. An isolation structure is arranged within the substrate and surrounds an upper surface of the substrate. The isolation structure includes one or more surfaces defining one or more trenches that are laterally between the isolation structure and the substrate. A conductive gate is over the substrate and laterally between a source region and a drain region disposed within the upper surface of the substrate. The conductive gate extends into the one or more trenches and has an upper surface that continuously extends past opposing sides of the one or more trenches.