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    Semiconductor package with underfill between a sensor coil and a semiconductor die
    13.
    发明授权
    Semiconductor package with underfill between a sensor coil and a semiconductor die 有权

    公开(公告)号：US11024576B1

    公开(公告)日：2021-06-01

    申请号：US16732296

    申请日：2019-12-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jeffrey Alan West ,  Byron Lovell Williams ,  Thomas Dyer Bonifield

    IPC: H01L23/522 ,  H01L23/498 ,  H01L43/04 ,  H01L21/48 ,  H01L21/56

    Abstract: A semiconductor package includes a leadframe including a sensor coil between sensor coil leads and further including a plurality of die leads physically and electrically separated from the sensor coil, and a semiconductor die over the leadframe with die contacts electrically connected to the die leads. The semiconductor die includes a sensor operable to detect magnetic fields created by electrical current through the sensor coil, the semiconductor die operable to output a signal representative of the detected magnetic fields via the die leads. The semiconductor package further includes a dielectric underfill filling a gap between the sensor coil and the semiconductor die, and a dielectric mold compound covering the sensor coil and the dielectric underfill and at least partially covering the semiconductor die and the die leads.

    METHODS AND APPARATUS FOR HIGH VOLTAGE INTEGRATED CIRCUIT CAPACITORS
    15.
    发明申请
    METHODS AND APPARATUS FOR HIGH VOLTAGE INTEGRATED CIRCUIT CAPACITORS 审中-公开

    公开(公告)号：US20170309702A1

    公开(公告)日：2017-10-26

    申请号：US15646465

    申请日：2017-07-11

    Applicant: Texas Instruments Incorporated

    Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

    IPC: H01L49/02

    CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/552 ,  H01L23/642 ,  H01L28/40 ,  H01L2224/48463 ,  H01L2224/49107

    Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

    METHODS AND APPARATUS FOR HIGH VOLTAGE INTEGRATED CIRCUIT CAPACITORS
    16.
    发明申请
    METHODS AND APPARATUS FOR HIGH VOLTAGE INTEGRATED CIRCUIT CAPACITORS 审中-公开
    高压集成电路电容器的方法和装置

    公开(公告)号：US20170062552A1

    公开(公告)日：2017-03-02

    申请号：US15348698

    申请日：2016-11-10

    Applicant: Texas Instruments Incorporated

    Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

    IPC: H01L49/02

    CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/552 ,  H01L23/642 ,  H01L28/40

    Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement. A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

    Abstract translation: 公开了高压集成电路电容器。 在一个例子中。 电容器结构包括半导体衬底; 底板，其具有覆盖在半导体衬底上的导电层; 沉积在所述底板的至少一部分上并且在第一区域中具有大于约6um的第一厚度的电容器电介质层; 在第一区域的边缘处的电容器电介质中的倾斜过渡区域，所述倾斜过渡区域具有从水平面倾斜大于5度的上表面，并且从第一区域延伸到电容器电介质的第二区域 层，其具有比第一厚度低的第二厚度; 以及形成在所述第一区域中覆盖所述电容器电介质层的至少一部分的顶板导体。 公开了方法和附加装置布置。

    High breakdown voltage microelectronic device isolation structure with improved reliability
    18.
    发明授权
    High breakdown voltage microelectronic device isolation structure with improved reliability 有权
    高击穿电压微电子器件隔离结构具有改进的可靠性

    公开(公告)号：US09299697B2

    公开(公告)日：2016-03-29

    申请号：US14277851

    申请日：2014-05-15

    Applicant: Texas Instruments Incorporated

    Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

    IPC: H01L27/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L49/02 ,  H01L29/06 ,  H01L21/8234

    CPC classification number: H01L28/91 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823481 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7833

    Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

    Abstract translation: 微电子器件包含具有高电压节点和低电压节点的高电压分量。 高电压节点通过微电子器件的基板的表面处的高压节点和低电压元件之间的主电介质与低电压节点隔离。 低压隙电介质层设置在高电压节点和主电介质之间。 低带隙电介质层含有至少一个带隙能量小于主电介质带隙能量的子层。 低带隙电介质层围绕高压节点连续延伸超过高压节点。 较低带隙电介质层具有围绕高电压节点的隔离断裂，距离高压节点的至少两倍于低带隙电介质层的厚度。

    Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies
    19.
    发明授权
    Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies 有权
    用于堆叠模具组件的复原晶片的激光辅助切割

    公开(公告)号：US08815642B2

    公开(公告)日：2014-08-26

    申请号：US14046486

    申请日：2013-10-04

    Applicant: Texas Instruments Incorporated

    Inventor： Jeffrey Alan West ,  Margaret Simmons-Matthews ,  Raymundo M. Camenforte

    IPC: H01L21/78 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56

    CPC classification number: H01L21/78 ,  H01L21/563 ,  H01L21/568 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.

    Abstract translation: 一种形成堆叠管芯器件的方法包括将第一半导体管芯附着到晶片上以形成重构的晶片，然后将第二半导体管芯接合到第一半导体管芯上，以在晶片上形成多个单独堆叠的管芯器件。 支撑带附接到第二半导体管芯的底部。 切割胶带附着在晶片上。 在将切割带安装到预定的切割通道之前或之后，将该晶片激光照射，该切割线与第一半导体管芯之间的间隙对准，以在期望的切割通道机械地削弱晶片，但不切割穿过晶片。 将切割带拉动以将晶片切割成多个单个部分，以通过切割带形成附接到单个晶片部分的多个单独堆叠的裸片器件。 在切割之前移除支撑带。

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