公开(公告)号：US20200312711A1

公开(公告)日：2020-10-01

申请号：US16901757

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Wen Hsu ,  Ming-Che Ku ,  Neng-Jye Yang ,  Yu-Wen Wang

IPC: H01L21/768 ,  H01L21/02

Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.

公开(公告)号：US12112953B2

公开(公告)日：2024-10-08

申请号：US18361027

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan Hsuan Hsu ,  Jao Sheng Huang ,  Yen-Chiu Kuo ,  Yu-Li Cheng ,  Ya Tzu Chen ,  Neng-Jye Yang ,  Chun-Li Chou

IPC: H01L21/67 ,  H01L21/02 ,  H01L21/311 ,  H01L21/68 ,  H01L21/687

CPC classification number: H01L21/31111 ,  H01L21/0206 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/31144 ,  H01L21/6708 ,  H01L21/68764

Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

公开(公告)号：US20240282575A1

公开(公告)日：2024-08-22

申请号：US18638436

申请日：2024-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Yao-Wen Hsu ,  Neng-Jye Yang ,  Li-Min Chen ,  Chia-Wei Wu ,  Kuan-Lin Chen ,  Kuo-Bin Huang

IPC: H01L21/027 ,  G03F7/09 ,  G03F7/095 ,  G03F7/20 ,  G03F7/32 ,  H01L21/02 ,  H01L21/033 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L21/0273 ,  G03F7/094 ,  G03F7/20 ,  G03F7/32 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31111 ,  G03F7/095 ,  H01L21/30608

Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.

公开(公告)号：US11942362B2

公开(公告)日：2024-03-26

申请号：US18178948

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Kuo-Bin Huang ,  Neng-Jye Yang ,  Li-Min Chen

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76823 ,  H01L21/02307 ,  H01L21/30604 ,  H01L21/4857 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

公开(公告)号：US11776818B2

公开(公告)日：2023-10-03

申请号：US17234119

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan Hsuan Hsu ,  Jao Sheng Huang ,  Yen-Chiu Kuo ,  Yu-Li Cheng ,  Ya Tzu Chen ,  Neng-Jye Yang ,  Chun-Li Chou

IPC: H01L21/67 ,  H01L21/311 ,  H01L21/02 ,  H01L21/687

CPC classification number: H01L21/31111 ,  H01L21/0206 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/31144 ,  H01L21/6708 ,  H01L21/68764

Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

公开(公告)号：US20220334473A1

公开(公告)日：2022-10-20

申请号：US17809912

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Min Chen ,  Kuo Bin Huang ,  Neng-Jye Yang ,  Chia-Wei Wu ,  Jian-Jou Lian

IPC: G03F7/00 ,  G03F7/075 ,  G03F7/09 ,  G03F7/16 ,  H01L21/027 ,  G03F7/42 ,  G03F1/80 ,  H01L21/02 ,  G03F7/20 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768

Abstract: A method includes forming a tri-layer. The tri-layer includes a bottom layer; a middle layer over the bottom layer; and a top layer over the middle layer. The top layer includes a photo resist. The method further includes removing the top layer; and removing the middle layer using a chemical solution. The chemical solution is free from potassium hydroxide (KOH), and includes at least one of a quaternary ammonium hydroxide and a quaternary ammonium fluoride.

公开(公告)号：US11378882B2

公开(公告)日：2022-07-05

申请号：US17007733

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Min Chen ,  Kuo Bin Huang ,  Neng-Jye Yang ,  Chia-Wei Wu ,  Jian-Jou Lian

IPC: G03F7/00 ,  G03F7/075 ,  G03F7/09 ,  G03F7/16 ,  H01L21/027 ,  G03F7/42 ,  G03F1/80 ,  H01L21/02 ,  G03F7/20 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768

Abstract: A method includes forming a tri-layer. The tri-layer includes a bottom layer; a middle layer over the bottom layer; and a top layer over the middle layer. The top layer includes a photo resist. The method further includes removing the top layer; and removing the middle layer using a chemical solution. The chemical solution is free from potassium hydroxide (KOH), and includes at least one of a quaternary ammonium hydroxide and a quaternary ammonium fluoride.

公开(公告)号：US20210287994A1

公开(公告)日：2021-09-16

申请号：US16814116

申请日：2020-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Chii-Ping Chen ,  Neng-Jye Yang ,  Ya-Lien Lee ,  An-Jiao Fu ,  Ya-Ching Tseng

IPC: H01L23/532 ,  H01L23/528

Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive structure is disposed within the first ILD layer. A capping layer continuously extends along a top surface of the lower conductive structure. An upper ILD structure overlies the lower conductive structure. A conductive body is disposed within the upper ILD structure. A bottom surface of the conductive body directly overlies the top surface of the lower conductive structure. A width of the bottom surface of the conductive body is less than a width of the top surface of the lower conductive structure. A diffusion barrier layer is disposed between the conductive body and the upper ILD structure. The diffusion barrier layer is laterally offset from a region disposed directly between the bottom surface of the conductive body and the top surface of the lower conductive structure by a non-zero distance.

公开(公告)号：US20240194522A1

公开(公告)日：2024-06-13

申请号：US18586925

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Kuo-Bin Huang ,  Neng-Jye Yang ,  Li-Min Chen

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L21/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76823 ,  H01L21/02307 ,  H01L21/30604 ,  H01L21/4857 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

公开(公告)号：US20230411210A1

公开(公告)日：2023-12-21

申请号：US18447889

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Cai-Ling Wu ,  Ya-Ching Tseng ,  Chii-Ping Chen ,  Neng-Jye Yang

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76834 ,  H01L21/76897 ,  H01L21/76883 ,  H01L23/53266 ,  H01L23/5226 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/7685

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.