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公开(公告)号：US20190096458A1
公开(公告)日：2019-03-28
申请号：US16205534
申请日：2018-11-30
发明人： Chih-Chieh CHIU , Chia-En HUANG , Fu-An WU , I-Han HUANG , Jung-Ping YANG
IPC分类号： G11C8/10 , G11C11/419 , G11C11/418 , G11C7/02 , G11C8/14
CPC分类号： G11C8/10 , G11C7/02 , G11C8/14 , G11C11/418 , G11C11/419
摘要： An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.
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公开(公告)号：US20160240245A1
公开(公告)日：2016-08-18
申请号：US14920209
申请日：2015-10-22
发明人： Hao-I YANG , Chia-En HUANG , Cheng Hung LEE , Geng-Cing LIN , Jung-Ping YANG
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/10 , G11C7/12 , G11C7/18 , G11C7/22 , G11C8/06 , G11C8/18 , H01L27/1104 , H01L27/1116
摘要： A circuit includes a first data line, a second data line, a first pulling device, a second pulling device, a third pulling device, and a fourth pulling device. The first pulling device is configured to be activated or deactivated responsive to a first control signal; and is configured to pull a first signal at the first data line toward a voltage level of a first voltage based on a second signal at the second data line when the first pulling device is activated. The second pulling device is configured to be activated or deactivated responsive to a second control signal; and is configured to pull the second signal at the second data line toward the voltage level of the first voltage based on the first signal at the first data line when the second pulling device is activated.
摘要翻译： 电路包括第一数据线，第二数据线，第一牵引装置，第二牵引装置，第三牵引装置和第四牵引装置。 第一牵引装置被配置为响应于第一控制信号被激活或停用; 并且被配置为当第一牵引装置被激活时，基于第二数据线处的第二信号将第一数据线处的第一信号拉向第一电压的电压电平。 第二牵引装置被配置为响应于第二控制信号被激活或停用; 并且被配置为当第二拉动装置被启动时，基于第一数据线处的第一信号将第二数据线处的第二信号拉向第一电压的电压电平。
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公开(公告)号：US20160019939A1
公开(公告)日：2016-01-21
申请号：US14870402
申请日：2015-09-30
CPC分类号： G11C7/12 , G11C7/106 , G11C7/1087 , G11C7/18 , G11C11/419 , G11C2207/005
摘要： A memory includes a plurality of memory blocks, a plurality of sensing circuits, a plurality of global bit lines, a common pre-charging circuit and a selection circuit. Each global bit line of the plurality of global bit lines is coupled to at least one of the memory blocks by a corresponding sensing circuit of the plurality of sensing circuits. The common pre-charging circuit is configured to individually pre-charge each global bit line of the plurality of global bit lines to a pre-charge voltage. The selection circuit is configured to selectively couple the common pre-charging circuit to a selected global bit line of the plurality of global bit lines.
摘要翻译： 存储器包括多个存储器块，多个感测电路，多个全局位线，公共预充电电路和选择电路。 多个全局位线的每个全局位线通过多个检测电路的对应检测电路耦合到至少一个存储器块。 公共预充电电路被配置为单独地将多个全局位线中的每个全局位线预充电为预充电电压。 选择电路被配置为选择性地将公共预充电电路耦合到多个全局位线的选定的全局位线。
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公开(公告)号：US20150092502A1
公开(公告)日：2015-04-02
申请号：US14039340
申请日：2013-09-27
发明人： Jung-Ping YANG , Chih-Chieh CHIU , Fu-An WU , Chia-En HUANG , I-Han HUANG
CPC分类号： G11C11/419 , G11C7/08 , G11C7/12 , G11C7/227
摘要： A circuit includes a tracking bit line, a tracking unit connected to the tracking bit line and a detection unit. The tracking unit is configured to receive a first control signal and configured to selectively charge or discharge a voltage on the tracking bit line in response to the first control signal. The detection unit is coupled to the tracking bit line and configured to generate a sense amplifier enable (SAE) signal in response to the voltage level on the tracking bit line.
摘要翻译： 电路包括跟踪位线，连接到跟踪位线的跟踪单元和检测单元。 跟踪单元被配置为接收第一控制信号并且被配置为响应于第一控制信号选择性地对跟踪位线进行充电或放电。 检测单元耦合到跟踪位线并且被配置为响应于跟踪位线上的电压电平产生读出放大器使能（SAE）信号。
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公开(公告)号：US20240331771A1
公开(公告)日：2024-10-03
申请号：US18741201
申请日：2024-06-12
发明人： Meng-Sheng Chang , Chia-En HUANG , Yi-Ching LIU , Yih WANG
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0026 , G11C13/0028 , G11C13/003
摘要： Disclosed herein are systems, methods and apparatuses related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.
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公开(公告)号：US20240331760A1
公开(公告)日：2024-10-03
申请号：US18743950
申请日：2024-06-14
发明人： Chieh LEE , Chia-En HUANG , Yi-Ching LIU , Wen-Chang CHENG , Yih WANG
IPC分类号： G11C11/4091 , G11C5/06 , G11C11/4094 , G11C11/4096 , H03K19/20
CPC分类号： G11C11/4091 , G11C5/063 , G11C11/4094 , G11C11/4096 , H03K19/20
摘要： A memory circuit includes a boundary layer, a first circuit positioned on a first side of the boundary layer and including a DRAM array including a plurality of DRAM cells, a second circuit positioned on a second side of the boundary layer opposite the first side and including a computation circuit, the computation circuit including a sense amplifier circuit, and a plurality of bit lines coupled to the plurality of DRAM cells and the sense amplifier circuit. Each bit line of the plurality of bit lines includes a via structure positioned in the boundary layer and the plurality of DRAM cells of the first circuit positioned on the first side of the boundary layer is an entirety of the DRAM cells of the memory circuit coupled to the sense amplifier circuit.
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公开(公告)号：US20240185895A1
公开(公告)日：2024-06-06
申请号：US18439982
申请日：2024-02-13
摘要： A system includes a high bandwidth memory (HBM) arranged into portions including memory cells, the HBM further including a differentiated dynamic voltage and frequency scaling (DDVFS) device to perform the following: for a first set of one or more of the memory cells in a first one of the portions, the first set including a first one of the memory cells, controlling a temperature of the first set based on one or more first environmental signals corresponding to at least a first transistor in the first memory cell; and for a second set of one or more of the memory cells in a second one of the portions, the second set including a second one of memory cells, controlling a temperature of the second set based on one or more second environmental signals corresponding to at least a second transistor in the second memory cell.
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公开(公告)号：US20230410851A1
公开(公告)日：2023-12-21
申请号：US18362270
申请日：2023-07-31
发明人： Haruki MORI , Chien-Chi TIEN , Chia-En HUANG , Hidehiro FUJIWARA , Yen-Huei CHEN , Feng-Lun CHEN
IPC分类号： G11C5/14 , G11C5/06 , H01L23/50 , H01L23/528
CPC分类号： G11C5/14 , H01L23/5286 , H01L23/50 , G11C5/06
摘要： Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.
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公开(公告)号：US20230354591A1
公开(公告)日：2023-11-02
申请号：US18346700
申请日：2023-07-03
发明人： Meng-Sheng CHANG , Chien-Ying CHEN , Chia-En HUANG , Yih WANG
IPC分类号： H10B20/20 , G06F30/392 , H01L23/522 , H01L23/528
CPC分类号： H10B20/20 , G06F30/392 , H01L23/5226 , H01L23/528
摘要： A method of generating an IC layout diagram includes abutting first and second cells to define a first active region including first and second anti-fuse bits, abutting third and fourth cells to define a second active region including third and fourth anti-fuse bits, and defining a third active region including fifth and sixth anti-fuse bits adjacent to the first through fourth anti-fuse bits. The first cell includes first and second via regions overlapping first and second gate regions shared by respective structures and transistors of the first, third, and fifth anti-fuse bits, the fourth cell includes third and fourth via regions overlapping third and fourth gate regions shared by respective transistors and structures of the second, fourth, and sixth anti-fuse bits, the third cell includes fifth and sixth via regions overlapping the first gate region, and the second cell includes seventh and eighth via regions overlapping the fourth gate region.
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公开(公告)号：US20230238303A1
公开(公告)日：2023-07-27
申请号：US17583415
申请日：2022-01-25
发明人： Meng-Han LIN , Chia-En HUANG , Yi-Ching LIU
IPC分类号： H01L23/48 , H01L23/522 , H01L23/528 , H01L27/11582 , H01L27/11519 , H01L27/11556 , H01L27/11565
CPC分类号： H01L23/481 , H01L23/5226 , H01L23/5283 , H01L27/11582 , H01L27/11519 , H01L27/11556 , H01L27/11565
摘要： A semiconductor device includes a substrate, an active structure, a memory structure, and a first conductive line. The active structure is disposed on the substrate. The memory structure is disposed over the active structure, and has a lower surface and an upper surface opposite to each other. The memory structure includes a deep via disposed in the memory structure, and extends in an upward direction from the lower surface to terminate at the upper surface. The first conductive line is disposed above the upper surface of the memory structure, and extends in a first lengthwise direction transverse to the upward direction. The first conductive line is electrically connected to the active structure through the deep via. A method for manufacturing the semiconductor device is also disclosed.
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