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    Methods and apparatus to DC couple LVDS driver to CML levels
    11.
    发明申请
    Methods and apparatus to DC couple LVDS driver to CML levels 有权
    将LVDS驱动程序直接耦合到CML级别的方法和设备

    公开(公告)号：US20060220681A1

    公开(公告)日：2006-10-05

    申请号：US11098832

    申请日：2005-04-04

    申请人： Wilson Wong ,  Tim Hoang ,  Sergey Shumarayev ,  Rakesh Patel ,  Simardeep Maangat

    发明人： Wilson Wong ,  Tim Hoang ,  Sergey Shumarayev ,  Rakesh Patel ,  Simardeep Maangat

    IPC分类号： H03K19/094

    CPC分类号： H03K19/017545

    摘要： Circuitry and methods are provided for an LVDS-like transmitter that may be able to DC couple to a receiver having a CML termination scheme. Replacing the common mode voltage source of an LVDS transmitter with a resistive pulldown to ground may allow the transmitter to interface in a DC coupled fashion with a CML receiver. Further, the resistive pulldown may be programmable. This LVDS-like transmitter may be able to support a wider customer base by allowing it to DC couple to a wider range of termination voltage levels, such as CML termination voltage levels.

    摘要翻译： 为能够将DC耦合到具有CML终止方案的接收机的类似LVDS的发射机提供电路和方法。 将具有电阻下拉到地的LVDS发射机的共模电压源替换可允许发射机以直流耦合方式与CML接收器接口。 此外，电阻下拉可以是可编程的。 这种类似LVDS的发射机可能能够通过允许其将DC耦合到更广泛的终止电压电平范围（例如CML终止电压电平）来支持更广泛的客户群。

    Heterogeneous transceiver architecture for wide range programmability of programmable logic devices
    14.
    发明申请
    Heterogeneous transceiver architecture for wide range programmability of programmable logic devices 有权
    异构收发器架构，用于可编程逻辑器件的广泛可编程性

    公开(公告)号：US20070237186A1

    公开(公告)日：2007-10-11

    申请号：US11402417

    申请日：2006-04-11

    申请人： Sergey Shumarayev ,  Bill Bereza ,  Chong Lee ,  Rakesh Patel ,  Wilson Wong

    发明人： Sergey Shumarayev ,  Bill Bereza ,  Chong Lee ,  Rakesh Patel ,  Wilson Wong

    IPC分类号： H04J3/04

    CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

    摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

    摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

    Programmable logic device architecture for accommodating specialized circuitry
    15.
    发明申请
    Programmable logic device architecture for accommodating specialized circuitry 失效
    用于容纳专用电路的可编程逻辑器件架构

    公开(公告)号：US20070063733A1

    公开(公告)日：2007-03-22

    申请号：US11230002

    申请日：2005-09-19

    申请人： Sergey Shumarayev ,  Rakesh Patel ,  Chong Lee

    发明人： Sergey Shumarayev ,  Rakesh Patel ,  Chong Lee

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17704 ,  H03K19/17732 ,  H03K19/17744

    摘要： A programmable logic device (PLD) having one or more programmable logic regions and one or more conventional input/output regions additionally has one or more peripheral areas including specialized circuitry. The peripheral specialized regions, which are not connected to the remainder of the programmable logic device (and may be made on separate dies from the remainder of the programmable logic device mounted on a common substrate), and one or both of the programmable logic regions and the conventional I/O regions, have contacts for metallization traces or other interconnections to connect the peripheral specialized regions to the remainder of the programmable logic device. The same PLD can be sold with or without the specialized circuitry capability by providing or not providing the interconnections. The peripheral specialized regions may include high-speed I/O (basic, up to about 3 Gbps, and enhanced, up to about 10-12 Gbps), as well as other types of specialized circuitry.

    摘要翻译： 具有一个或多个可编程逻辑区域和一个或多个常规输入/输出区域的可编程逻辑器件（PLD）还具有包括专用电路的一个或多个外围区域。 外围专用区域不连接到可编程逻辑器件的其余部分（并且可以在与安装在公共衬底上的可编程逻辑器件的其余部分分开的管芯上）制造，以及一个或两个可编程逻辑区域 常规I / O区域具有用于金属化迹线或其它互连的触点，以将外围专用区域连接到可编程逻辑器件的其余部分。 通过提供或不提供互连，可以在具有或不具有专用电路能力的情况下出售相同的PLD。 外围专业区域可能包括高速I / O（基本，高达约3 Gbps，增强，高达10-12 Gbps）以及其他类型的专用电路。

    On-chip eye viewer architecture for highspeed transceivers
    17.
    发明授权
    On-chip eye viewer architecture for highspeed transceivers 有权
    用于高速收发器的片上眼睛查看器架构

    公开(公告)号：US08744012B1

    公开(公告)日：2014-06-03

    申请号：US13369108

    申请日：2012-02-08

    申请人： Weiqi Ding ,  Mingde Pan ,  Sergey Shumarayev ,  Peng Li

    发明人： Weiqi Ding ,  Mingde Pan ,  Sergey Shumarayev ,  Peng Li

    IPC分类号： H03K9/00

    CPC分类号： H04L1/203 ,  G01R31/31711

    摘要： System, methods, and devices for determining an eye diagram of a serial input signal to an integrated circuit without an oscilloscope are provided. For example, one embodiment of an integrated circuit device may be capable of determining an eye diagram associated with a serial input signal either during or after equalization. The device may include an equalizer and eye viewer circuitry configured to select a node of the equalizer for eye monitoring of the input signal, which may be during or after equalization. In one embodiment, the eye viewer circuitry may provide a separate sampler for each respective node, while sharing a control logic and phase interpolator among the samplers. The eye viewer circuitry may determine horizontal and vertical boundaries of the eye diagram associated with the serial input signal, as seen from the selected node of the equalizer.

    摘要翻译： 提供了用于确定没有示波器的集成电路的串行输入信号的眼图的系统，方法和设备。 例如，集成电路器件的一个实施例可能能够在均衡期间或之后确定与串行输入信号相关联的眼图。 该装置可以包括均衡器和眼睛观察器电路，其被配置为选择均衡器的节点，用于在均衡期间或之后的输入信号的眼睛监视。 在一个实施例中，眼睛观察器电路可以为每个相应节点提供单独的采样器，同时在采样器之间共享控制逻辑和相位插值器。 从均衡器的选定节点看，眼睛观察器电路可以确定与串行输入信号相关联的眼图的水平和垂直边界。

    Simulation tool for high-speed communications links
    18.
    发明授权
    Simulation tool for high-speed communications links 有权
    用于高速通信链接的仿真工具

    公开(公告)号：US08626474B2

    公开(公告)日：2014-01-07

    申请号：US12762848

    申请日：2010-04-19

    申请人： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

    发明人： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

    IPC分类号： G06F7/60 ,  G06G7/62 ,  G06F17/50

    CPC分类号： G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

    摘要： A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

    摘要翻译： 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。 链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

    Phase-locked loop architecture and clock distribution system
    19.
    发明授权
    Phase-locked loop architecture and clock distribution system 有权
    锁相环架构和时钟分配系统

    公开(公告)号：US08542042B1

    公开(公告)日：2013-09-24

    申请号：US13532528

    申请日：2012-06-25

    申请人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff

    发明人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff

    IPC分类号： H03L7/06

    CPC分类号： H03L7/23 ,  G06F1/10 ,  H03L7/0807 ,  H03L7/183 ,  H03L7/197 ,  H03L7/1974 ,  H04L7/0331

    摘要： One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及一种可断裂的PLL电路。 断裂PLL电路包括产生第一频率输出的第一锁相环电路，第二锁相环电路; 布置成产生第二频率输出和多个共享输出资源。 可重构电路被布置成使得第一和第二频率输出中的任一个可由多个共享输出资源中的每一个接收。 另一实施例涉及一种集成电路，其包括多个PMA模块，多个多用途PLL电路和可编程时钟网络。 可编程时钟网络被布置为允许由多用途PLL电路输出的时钟信号被PMA模块选择性地用于收发器应用或由用于非收发器应用的其它电路。 还公开了其它实施例和特征。

    Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations
    20.
    发明授权
    Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations 有权
    用于执行或促进示波器，抖动和/或误码率测试仪操作的集成电路的电路

    公开(公告)号：US08504882B2

    公开(公告)日：2013-08-06

    申请号：US12884305

    申请日：2010-09-17

    申请人： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Siriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

    发明人： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Siriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

    IPC分类号： G06F11/00

    CPC分类号： G06F11/267

    摘要： An integrated circuit (“IC”) includes circuitry for use in testing a serial data signal. One such IC includes circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. One such IC also includes circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. Such an IC provides output signals indicative of results of its operations. One such IC operates in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

    摘要翻译： 集成电路（“IC”）包括用于测试串行数据信号的电路。 一个这样的IC包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度来发送串行数据信号的电路。 一个这样的IC还包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 这样的IC提供指示其操作结果的输出信号。 一个这样的IC以各种模式运行，以执行或至少模拟示波器，误码率测试仪等的功能，用于测试关于抖动容差，噪声容限等的信号和电路。