公开(公告)号：US08018017B2

公开(公告)日：2011-09-13

申请号：US10905905

申请日：2005-01-26

Applicant: Fen Chen ,  Cathryn J. Christiansen ,  Richard S. Kontra ,  Tom C. Lee ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Joseph E. Therrien

Inventor： Fen Chen ,  Cathryn J. Christiansen ,  Richard S. Kontra ,  Tom C. Lee ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Joseph E. Therrien

IPC: H01L31/058

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.

Abstract translation: 提供了一种热机械可切割结构，可用作集成电路的可编程保险丝。 如应用于可编程保险丝，热机械可切割结构包括与热机械应力源相邻的导电可切割层。 当电通过可切割层时，可切割层和热机械应力器被加热并且气体从热机械应力源逸出。 气体将热机械应力局部绝缘，导致邻近热机械应力的气泡局部熔化，形成裂开位置的可切割结构。 熔化还中断当前通过可切割结构的流动，因此可切割结构冷却和收缩。 热机械应力还由于由其产生的气体引起的相变而收缩。 当热机械可裂解结构冷却时，裂解位置膨胀，导致间隙永久形成。

公开(公告)号：US20110140271A1

公开(公告)日：2011-06-16

申请号：US12634741

申请日：2009-12-10

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L24/11 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13618 ,  H01L2224/1362 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

Abstract translation: 公开了一种用改进的导电焊盘形成芯片的芯片和方法，其允许与芯片载体或另一个集成电路芯片的柔性C4连接。 垫具有三维几何形状（例如，金字塔或锥形），其具有与芯片表面相邻的基部，与基部相对的顶点以及可选地在顶点顶部的蘑菇形帽。 每个焊盘可以包括单层导电材料或多层导电材料（例如，堆叠在非润湿层上方的润湿层）。 焊盘可以被暴露以允许随后连接到芯片载体或第二芯片上的相应焊料凸块。 或者，焊球可以定位在导电焊盘上，以允许随后连接到芯片载体或第二芯片上相应的焊膏填充的开口。

公开(公告)号：US07871919B2

公开(公告)日：2011-01-18

申请号：US12344802

申请日：2008-12-29

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05556 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming a plurality of trenches in a dielectric layer extending to an underlying metal layer. The method further includes depositing metal in the plurality of trenches to form discrete metal line islands in contact with the underlying metal layer. The method also includes forming a solder bump in electrical connection to the plurality of metal line islands.

Abstract translation: 具有改善的焊料凸点连接的结构和制造这种结构的方法在本文中提供。 该方法包括在延伸到下面的金属层的电介质层中形成多个沟槽。 该方法还包括在多个沟槽中沉积金属以形成与下面的金属层接触的离散金属线岛。 该方法还包括形成与多个金属线岛电连接的焊料凸块。

公开(公告)号：US07868453B2

公开(公告)日：2011-01-11

申请号：US12032158

申请日：2008-02-15

Applicant: Timothy Harrison Daubenspeck ,  Timothy D. Sullivan

Inventor： Timothy Harrison Daubenspeck ,  Timothy D. Sullivan

IPC: H01L23/52

CPC classification number: H01L23/488 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45147 ,  H01L2224/48824 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad.

Abstract translation: 制作结构的结构和方法。 所述结构包括结构，包括：在衬底上延伸的有机介电钝化层; 在所述有机介电钝化层的顶表面上的导电电流扩散焊盘; 导电焊料凸块焊盘，其在电流扩散焊盘的顶表面上包括一层或多层; 以及包含锡的导电焊料凸块，所述焊料凸块在所述焊料凸块焊盘的顶表面上，所述电流扩散焊盘包括一个或多个层，所述一个或多个层中的至少一个由不会形成 金属间化合物与锡或一层或多层中的至少一层是对锡的扩散阻挡层并且与焊料凸块相邻的材料。

公开(公告)号：US07692439B2

公开(公告)日：2010-04-06

申请号：US12154304

申请日：2008-05-22

Applicant: Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

Inventor： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

IPC: G01R31/02 ,  H01L23/58 ,  G01N25/20

CPC classification number: G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.

Abstract translation: 提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平 延伸平面 该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。 下导电或半导体元件可以与下通孔的底端接触。 上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。 上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。 该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

公开(公告)号：US20100032835A1

公开(公告)日：2010-02-11

申请号：US12188235

申请日：2008-08-08

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Timothy D. Sullivan

IPC: H01L23/488 ,  H01L21/44

CPC classification number: H01L24/11 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/13028 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433

Abstract: The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in solder bumps and related structures. A semiconductor structure includes a wire comprising first and second wire segments, a pad formed over the wire, and a ball limiting metallization (BLM) layer formed over the pad. The semiconductor structure also includes a solder bump formed over the BLM layer, a terminal via formed over the BLM layer, and at least one peripheral via formed between the second wire segment and the pad. The first and second wire segments are discrete wire segments.

Abstract translation: 本发明一般涉及半导体器件，更具体地涉及用于增强焊料凸点和相关结构中的电迁移（EM）性能的结构和方法。 半导体结构包括包括第一和第二线段的线，在线上形成的焊盘以及形成在焊盘上的球限制金属化（BLM）层。 半导体结构还包括形成在BLM层上的焊料凸块，在BLM层上形成的端子通孔，以及形成在第二线段和焊盘之间的至少一个外围通孔。 第一和第二线段是分立的线段。

公开(公告)号：US07231617B2

公开(公告)日：2007-06-12

申请号：US10711418

申请日：2004-09-17

Applicant: Fen Chen ,  Jeffrey P. Gambino ,  Jason P. Gill ,  Baozhen Li ,  Timothy D. Sullivan

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Jason P. Gill ,  Baozhen Li ,  Timothy D. Sullivan

IPC: G06F17/50

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines can be formed on a wafer each of which comprises multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections of all the lines. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments can be determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.

Abstract translation: 用于评估半导体集成电路中的线路的新型结构和方法。 可以在每个包括多个线段的晶片上形成第一组多条线。 所有线段长度相同。 测量线路段的电阻。 然后，基于所有线的所有部分的电阻来确定第一线几何形状调整。 第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。 相同长度和厚度的第二组多条线可以形成在同一晶片上。 然后，可以基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。 第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

公开(公告)号：US07173338B2

公开(公告)日：2007-02-06

申请号：US10708486

申请日：2004-03-06

Applicant: Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

Inventor： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

IPC: H01L23/48

CPC classification number: H01L21/7684 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

Abstract translation: 用于抑制半导体加工中的局部金属沉淀形成（LMPF）的方法和结构。 对于暴露于制造环境并且电耦合到N区域的每个金属线，至少一个P +区形成为电耦合到相同的金属线。 结果，几乎没有多余的电子可用于与金属离子结合以在金属线上形成局部金属沉淀。 可以在金属线周围形成监测斜坡端子并与金属线电断开。 通过向金属线和监视斜坡端子施加电压差并测量流过金属线和监视斜坡端子的所得电流，可以确定在金属线处是否形成了局部金属沉淀物。

公开(公告)号：US07096450B2

公开(公告)日：2006-08-22

申请号：US10604165

申请日：2003-06-28

Applicant: Jason P. Gill ,  David L. Harmon ,  Deborah M. Massey ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Junichi Furukawa

Inventor： Jason P. Gill ,  David L. Harmon ,  Deborah M. Massey ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Junichi Furukawa

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  H01L23/3677 ,  H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  H05K1/0201 ,  H05K3/0005 ,  H01L2924/00

Abstract: An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.

公开(公告)号：US06995392B2

公开(公告)日：2006-02-07

申请号：US10214546

申请日：2002-08-07

Applicant: Paul S. McLaughlin ,  Timothy D. Sullivan ,  Ping-Chuan Wang

Inventor： Paul S. McLaughlin ,  Timothy D. Sullivan ,  Ping-Chuan Wang

IPC: H01L23/58

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A test structure is disclosed for locating electromigration voids in a semiconductor interconnect structure having an interconnect via interconnecting a lower metallization line with an upper metallization line. In an exemplary embodiment, the test structure includes a via portion the top of the interconnect via at the upper metallization line. In addition, a line portion extends from the via portion, wherein the line portion connects to an external probing surface, in addition to a probing surface on the lower metallization line, thereby allowing the identification of any electromigration voids present in the interconnect via.

Abstract translation: 公开了一种测试结构，用于通过将下部金属化线与上部金属化线相互连接来定位具有互连的半导体互连结构中的电迁移空穴。 在示例性实施例中，测试结构包括在上金属化线处的互连通孔的顶部的通孔部分。 此外，线路部分从通孔部分延伸，其中线部分连接到外部探测表面，以及下部金属化线上的探测表面，从而允许识别互连通孔中存在的任何电迁移空隙。