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公开(公告)号：US20110094779A1
公开(公告)日：2011-04-28
申请号：US12718194
申请日：2010-03-05
Applicant: Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
Inventor： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
CPC classification number: H05K3/184 , H05K3/0032 , H05K3/387 , H05K3/421 , H05K3/465 , H05K3/4661 , H05K2201/0195 , H05K2201/0347 , H05K2203/107 , H05K2203/1173
Abstract: A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer.
Abstract translation: 提供了包括电路板，绝缘层，导电通孔，可镀介电层和导电图案的电路结构。 绝缘层设置在电路板上并覆盖电路板的电路层。 导电通孔穿过绝缘层并连接电路层并从绝缘层的表面突出。 具有沟槽图案的可镀介电层设置在绝缘层的表面上，其中从表面突出的导电通孔的部分位于沟槽图案中。 可镀介电层的材料包括化学镀层材料。 导电图案处于沟槽图案中并且连接导电通孔，其中在导电图案和导电通孔之间存在界面，并从绝缘层的表面突出。
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12.发明申请公开(公告)号：US20110023297A1
公开(公告)日：2011-02-03
申请号：US12902518
申请日：2010-10-12
Applicant: Ming-Huan Yang , Chung-Wei Wang , Chia-Chi Wu , Chao-Kai Cheng , Tzyy-Jang Tseng , Chang-Ming Lee , Cheng-Po Yu , Cheng-Hung Yu
Inventor： Ming-Huan Yang , Chung-Wei Wang , Chia-Chi Wu , Chao-Kai Cheng , Tzyy-Jang Tseng , Chang-Ming Lee , Cheng-Po Yu , Cheng-Hung Yu
IPC: H05K3/10
CPC classification number: H05K3/182 , H05K3/389 , H05K3/421 , H05K3/422 , H05K3/426 , H05K3/4661 , H05K2203/013 , H05K2203/0565 , H05K2203/0709 , Y10T29/49155
Abstract: A method for fabricating a double-sided or multi-layer printed circuit board (PCB) by ink jet printing that includes providing a substrate, forming a first self-assembly membrane (SAM) on at least one side of the substrate, forming a non-adhesive membrane on the first SAM, forming at least one microhole in the substrate, forming a second SAM on a surface of the microhole, providing catalyst particles on the at least one side of the substrate and on the surface of the microhole, and forming a catalyst circuit pattern on the substrate.
Abstract translation: 一种通过喷墨印刷制造双面或多层印刷电路板（PCB）的方法，其包括提供基板，在所述基板的至少一侧上形成第一自组装膜（SAM），形成非 - 在第一SAM上形成粘合膜，在基底中形成至少一个微孔，在微孔的表面上形成第二SAM，在基底的至少一侧和微孔的表面上形成催化剂颗粒，并形成 基板上的催化剂电路图案。
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公开(公告)号：US20090197364A1
公开(公告)日：2009-08-06
申请号：US12422428
申请日：2009-04-13
Applicant: Tzyy-Jang Tseng , Chih-Ming Chang , Cheng-Po Yu , Chung W. Ho
Inventor： Tzyy-Jang Tseng , Chih-Ming Chang , Cheng-Po Yu , Chung W. Ho
CPC classification number: H01L23/142 , H01L21/6835 , H01L33/486 , H01L33/62 , H01L33/642 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/181 , H05K3/06 , H05K3/202 , H05K2201/09881 , H05K2203/0369 , H05K2203/1476 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
Abstract: A method of fabricating a substrate includes following steps. First, a metallic panel having a first surface and a second surface is provided. A first half-etching process is carried out to etch the first surface of the metallic panel to a first depth so that a first patterned metallic layer is formed on the first surface. Next, a first insulating material is deposited into gaps in the first patterned metallic layer to form a first insulator. Thereafter, a second half-etching process is carried out to etch the second surface of the metallic panel to a second depth and expose at least a portion of the first insulator so that a second patterned metallic layer is formed on the second surface. The first depth and the second depth together equal the thickness of the metallic panel.
Abstract translation: 制造衬底的方法包括以下步骤。 首先，提供具有第一表面和第二表面的金属板。 执行第一半蚀刻工艺以将金属板的第一表面蚀刻到第一深度，使得在第一表面上形成第一图案化金属层。 接下来，将第一绝缘材料沉积在第一图案化金属层中的间隙中以形成第一绝缘体。 此后，执行第二半蚀刻工艺以将金属板的第二表面蚀刻到第二深度，并且暴露第一绝缘体的至少一部分，使得在第二表面上形成第二图案化金属层。 第一深度和第二深度一起等于金属面板的厚度。
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公开(公告)号：US20070099123A1
公开(公告)日：2007-05-03
申请号：US11307425
申请日：2006-02-07
Applicant: Tzyy-Jang Tseng , Cheng-Po Yu
Inventor： Tzyy-Jang Tseng , Cheng-Po Yu
IPC: G03C5/00
CPC classification number: H05K3/28 , H05K3/3452 , H05K2203/013 , H05K2203/0557 , H05K2203/058 , H05K2203/1476
Abstract: A method of forming solder mask, suitable for forming a solder mask on the surface of a wiring board, is provided. The surface of the wiring board includes a first region and a second region, and the surface of the wiring board has a wiring pattern thereon. The method includes forming a first sub solder mask in the first region on the surface of the wiring board by performing a screen-printing or a photolithographic process, and forming a second sub solder mask in the second region on the surface of the wiring board by performing an ink-jet printing process. The method not only improves the precision of the solder mask alignment on the wiring board and its reliability, but also increases the production rate and lowers the manufacturing cost.
Abstract translation: 提供一种形成焊接掩模的方法，该方法适用于在布线板的表面上形成焊接掩模。 布线板的表面包括第一区域和第二区域，并且布线板的表面上具有布线图案。 该方法包括通过丝网印刷或光刻工艺在布线板的表面上的第一区域中形成第一子焊料掩模，并且在布线板的表面上的第二区域中形成第二副焊料掩模 进行喷墨打印处理。 该方法不仅提高了布线板上的焊盘对准的精度及其可靠性，而且提高了生产率，降低了制造成本。
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公开(公告)号：US08161638B2
公开(公告)日：2012-04-24
申请号：US12783806
申请日：2010-05-20
Applicant: Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
Inventor： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
IPC: H01K3/10
CPC classification number: H05K3/465 , H05K3/0032 , H05K3/0035 , H05K3/184 , H05K3/421 , H05K3/4661 , H05K2201/0166 , H05K2201/0195 , H05K2203/1152 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T156/1056
Abstract: A manufacturing method of circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board and an insulating layer disposed therebetween are provided. The composite dielectric layer includes a non-platable dielectric layer and a platable dielectric layer between the non-platable dielectric layer and the insulating layer wherein the non-platable dielectric layer includes a chemical non-platable material and the platable dielectric layer includes a chemical platable material. Then, the composite dielectric layer, the circuit board and the insulating layer are compressed. Subsequently, a through hole passing through the composite dielectric layer and the insulating layer is formed and a conductive via connecting a circuit layer of the circuit board is formed therein. Then, a trench pattern passing through the non-platable dielectric layer is formed on the composite dielectric layer. Subsequently, a chemical plating process is performed to form a conductive pattern in the trench pattern.
Abstract translation: 电路结构的制造方法如下所述。 首先，提供复合电介质层，电路基板和设置在它们之间的绝缘层。 复合电介质层包括不可镀介电层和介于非平板电介质层和绝缘层之间的可镀介电层，其中非可镀介电层包括化学不可镀材料，并且可镀介电层包括化学镀层 材料。 然后，复合介电层，电路板和绝缘层被压缩。 随后，形成穿过复合介电层和绝缘层的通孔，并且在其中形成连接电路板的电路层的导电通孔。 然后，在复合电介质层上形成通过非电介质层的沟槽图案。 随后，执行化学镀处理以在沟槽图案中形成导电图案。
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Patent Agency Ranking
公开(公告)号：US20110100543A1
公开(公告)日：2011-05-05
申请号：US12783806
申请日：2010-05-20
Applicant: Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
Inventor： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
CPC classification number: H05K3/465 , H05K3/0032 , H05K3/0035 , H05K3/184 , H05K3/421 , H05K3/4661 , H05K2201/0166 , H05K2201/0195 , H05K2203/1152 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T156/1056
Abstract: A manufacturing method of circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board and an insulating layer disposed therebetween are provided. The composite dielectric layer includes a non-platable dielectric layer and a platable dielectric layer between the non-platable dielectric layer and the insulating layer wherein the non-platable dielectric layer includes a chemical non-platable material and the platable dielectric layer includes a chemical platable material. Then, the composite dielectric layer, the circuit board and the insulating layer are compressed. Subsequently, a through hole passing through the composite dielectric layer and the insulating layer is formed and a conductive via connecting a circuit layer of the circuit board is formed therein. Then, a trench pattern passing through the non-platable dielectric layer is formed on the composite dielectric layer. Subsequently, a chemical plating process is performed to form a conductive pattern in the trench pattern.
Abstract translation: 电路结构的制造方法如下所述。 首先，提供复合电介质层，电路基板和设置在它们之间的绝缘层。 复合电介质层包括不可镀介电层和介于非平板电介质层和绝缘层之间的可镀介电层，其中非可镀介电层包括化学不可镀材料，并且可镀介电层包括化学镀层 材料。 然后，复合介电层，电路板和绝缘层被压缩。 随后，形成穿过复合介电层和绝缘层的通孔，并且在其中形成连接电路板的电路层的导电通孔。 然后，在复合电介质层上形成通过非电介质层的沟槽图案。 随后，执行化学镀处理以在沟槽图案中形成导电图案。
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17.发明申请公开(公告)号：US20070263862A1
公开(公告)日：2007-11-15
申请号：US11465814
申请日：2006-08-21
Applicant: Tzyy-Jang Tseng , Cheng-Po Yu , Chi-Min Chang , Cheng-Hung Yu
Inventor： Tzyy-Jang Tseng , Cheng-Po Yu , Chi-Min Chang , Cheng-Hung Yu
IPC: G09C3/08
CPC classification number: H05K1/0269 , H05K3/0097 , H05K3/225 , H05K2201/09936 , H05K2203/013
Abstract: A manufacturing process and an apparatus for printing imprint on defective board are provided. An automatic printing device is used for replacing operator, so as to reduce manpower and to increase the correctness and veracity of defect mark printing. The manufacturing process includes the following steps: first, an image sensor captures an image of a defect mark and transmits the image to a processing unit for data processing. Next, the data is compared, and an inkjet head is notified of the correct printing position to print ink on the customer identification mark of the printed circuit board.
Abstract translation: 提供了制造工艺和用于在缺陷板上印刷压印的装置。 使用自动打印装置来代替操作者，以减少人力和提高缺陷标记打印的正确性和真实性。 制造过程包括以下步骤：首先，图像传感器捕获缺陷标记的图像，并将图像发送到用于数据处理的处理单元。 接下来，比较数据，并且通知喷墨头正确的打印位置以在印刷电路板的客户识别标记上印刷墨水。
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18.发明申请公开(公告)号：US20070087457A1
公开(公告)日：2007-04-19
申请号：US11164855
申请日：2005-12-08
Applicant: Tzyy-Jang Tseng , Cheng-Po Yu
Inventor： Tzyy-Jang Tseng , Cheng-Po Yu
IPC: H01L21/00
CPC classification number: H05K3/225 , H05K1/0269 , H05K3/0032 , H05K3/064 , H05K2203/013
Abstract: A method for inspecting and mending defects of photo-resist is provided. It includes the following steps. First, a substrate having at least one film is provided. Then, a patterned photo-resist layer is formed on the film. Next, an optical inspection procedure is performed to inspect whether the patterned photo-resist layer has defects or not. If the patterned photo-resist layer has defects, the defects are classified into gaps and protrusions and then the gaps and the protrusions are positioned. If the patterned photo-resist layer has defects such as gaps, an ink-jet printing method, for example, is performed on the patterned photo-resist layer to fill the gaps up. If the patterned photo-resist layer has defects such as protrusions, a laser method, for example, is performed on the patterned photo-resist layer to remove the protrusions. So the defects of the patterned photo-resist layer can be mended.
Abstract translation: 提供了一种检查和修补光刻胶缺陷的方法。 它包括以下步骤。 首先，提供具有至少一个膜的基板。 然后，在膜上形成图案化的光致抗蚀剂层。 接下来，执行光学检查程序以检查图案化的光致抗蚀剂层是否具有缺陷。 如果图案的光致抗蚀剂层具有缺陷，则将缺陷分为间隙和突起，然后定位间隙和突起。 如果图案化的光致抗蚀剂层具有诸如间隙的缺陷，则在图案化的光致抗蚀剂层上进行例如喷墨打印方法来填充间隙。 如果图案化的光致抗蚀剂层具有诸如突起的缺陷，则在图案化的光致抗蚀剂层上执行例如激光方法以去除突起。 因此，可以修补图案化光致抗蚀剂层的缺陷。
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公开(公告)号：US20120031652A1
公开(公告)日：2012-02-09
申请号：US13050009
申请日：2011-03-17
Applicant: TZYY-JANG TSENG , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
Inventor： TZYY-JANG TSENG , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
CPC classification number: H05K3/12 , C23C18/1605 , C23C18/165 , C25D5/022 , H05K1/0203 , H05K1/056 , H05K3/02 , H05K3/181 , H05K3/188 , H05K3/3436 , H05K2201/0187 , Y10T29/302 , Y10T29/49155 , Y10T156/10
Abstract: A circuit board includes a metal pattern layer, a thermally conductive plate, an electrically insulating layer, and at least one electrically insulating material. The thermally conductive plate has a plane. The electrically insulating layer is disposed between the metal pattern layer and the plane and partially covers the plane. The electrically insulating material covers the plane where is not covered by the electrically insulating layer and touches the thermally conductive plate. The electrically insulating layer exposes the electrically insulating material, and a thermal conductivity of the electrically insulating material is larger than a thermal conductivity of the electrically insulating layer.
Abstract translation: 电路板包括金属图案层，导热板，电绝缘层和至少一个电绝缘材料。 导热板具有平面。 电绝缘层设置在金属图案层和平面之间并且部分覆盖平面。 电绝缘材料覆盖未被电绝缘层覆盖并接触导热板的平面。 电绝缘层暴露电绝缘材料，并且电绝缘材料的热导率大于电绝缘层的热导率。
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公开(公告)号：US20070153488A1
公开(公告)日：2007-07-05
申请号：US11554882
申请日：2006-10-31
Applicant: Ming-Huan Yang , Chung-Wei Wang , Chia-Chi Wu , Chao-Kai Cheng , Tzyy-Jang Tseng , Chang-Ming Lee , Cheng-Po Yu , Cheng-Hung Yu
Inventor： Ming-Huan Yang , Chung-Wei Wang , Chia-Chi Wu , Chao-Kai Cheng , Tzyy-Jang Tseng , Chang-Ming Lee , Cheng-Po Yu , Cheng-Hung Yu
CPC classification number: H05K3/182 , H05K3/389 , H05K3/421 , H05K3/422 , H05K3/426 , H05K3/4661 , H05K2203/013 , H05K2203/0565 , H05K2203/0709 , Y10T29/49155
Abstract: A method for fabricating a double-sided or multi-layer printed circuit board (PCB) by ink-jet printing that includes providing a substrate, forming a first self-assembly membrane (SAM) on at least one side of the substrate, forming a non-adhesive membrane on the first SAM, forming at least one microhole in the substrate, forming a second SAM on a surface of the microhole, providing catalyst particles on the at least one side of the substrate and on the surface of the microhole, and forming a catalyst circuit pattern on the substrate.
Abstract translation: 一种通过喷墨印刷制造双面或多层印刷电路板（PCB）的方法，其包括提供基板，在所述基板的至少一侧上形成第一自组装膜（SAM），形成 在所述第一SAM上形成非粘性膜，在所述基底中形成至少一个微孔，在所述微孔的表面上形成第二SAM，在所述基底的至少一侧和所述微孔的表面上提供催化剂颗粒，以及 在基板上形成催化剂电路图案。
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