公开(公告)号：US09455351B1

公开(公告)日：2016-09-27

申请号：US14841731

申请日：2015-09-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Chun-Yuan Wu

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/66969

Abstract: An oxide semiconductor field effect transistor (OS FET) device includes a first dielectric layer formed on a substrate, an oxide semiconductor (OS) island formed on the first dielectric layer, a first gate electrode formed on the OS island, a gate dielectric layer formed in between the first gate electrode and the OS island, a patterned hard mask layer formed on a top surface of the first gate electrode, an etch stop layer covering a top surface of the patterned hard mask layer and sidewalls of the first gate electrode, and a source electrode and a drain electrode formed on the OS island. At least one of the source electrode and the drain electrode partially overlaps the etching stop layer on the sidewalls of the first gate electrode.

Abstract translation: 一种氧化物半导体场效应晶体管（OS FET）器件包括形成在基板上的第一介电层，形成在第一介电层上的氧化物半导体（OS）岛，形成在OS岛上的第一栅电极，形成的栅介质层 在第一栅电极和OS岛之间，形成在第一栅电极的顶表面上的图案化硬掩模层，覆盖图案化硬掩模层的顶表面和第一栅电极的侧壁的蚀刻停止层，以及 形成在OS岛上的源电极和漏电极。 源极电极和漏极电极中的至少一个部分地与第一栅电极的侧壁上的蚀刻停止层重叠。

公开(公告)号：US09305994B2

公开(公告)日：2016-04-05

申请号：US14445416

申请日：2014-07-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L28/60

Abstract: A semiconductor apparatus including a stacked capacitance structure is provided. The stacked capacitance structure includes a first inner metal layer having a first pad area adjacent to an edge of the first inner metal layer, a first insulating layer disposed on the first inner metal layer and exposing the first pad area, a second inner metal layer disposed on the first insulating layer and having a second pad area adjacent to an edge of the second inner metal layer, a second insulating layer disposed on the second inner metal layer and exposing the second pad area, and a third inner metal layer covering the second inner metal layer and including at least one first slit. The first pad area and the second pad area include a plurality of pads. The first slit corresponds to the second pad area, such that the pads on the second pad area are exposed.

Abstract translation: 提供了包括堆叠电容结构的半导体装置。 堆叠的电容结构包括具有与第一内金属层的边缘相邻的第一焊盘区域的第一内部金属层，设置在第一内部金属层上并暴露第一焊盘区域的第一绝缘层，设置的第二内部金属层 在第一绝缘层上并且具有与第二内金属层的边缘相邻的第二焊盘区域，设置在第二内金属层上并暴露第二焊盘区域的第二绝缘层，以及覆盖第二内金属层的第三内金属层 金属层并且包括至少一个第一狭缝。 第一焊盘区域和第二焊盘区域包括多个焊盘。 第一狭缝对应于第二焊盘区域，使得第二焊盘区域上的焊盘露出。

公开(公告)号：US20150264813A1

公开(公告)日：2015-09-17

申请号：US14204898

申请日：2014-03-11

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H05K1/18 ,  H05K3/46 ,  H05K1/02 ,  H05K1/16 ,  H05K1/11

CPC classification number: H05K1/162 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5223 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4673 ,  H05K2201/0179 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2201/10378

Abstract: A chip-stack interposer structure including a passive device is described, including an interposing layer, a capacitor, a first contact and a second contact. The capacitor is embedded in or disposed on the interposing layer, including a first electrode, a second electrode and a dielectric layer between the first and the second electrodes. The first contact is connected with the first electrode. The second contact is connected with the second electrode. The first electrode and the second electrode are disposed at the same side of the interposing layer or at different sides of the interposing layer.

Abstract translation: 描述包括无源器件的芯片堆叠插入器结构，包括中介层，电容器，第一接触和第二接触。 电容器嵌入或设置在插入层上，包括在第一和第二电极之间的第一电极，第二电极和介电层。 第一触点与第一电极连接。 第二触点与第二电极连接。 第一电极和第二电极设置在插入层的相同侧或者插入层的不同侧。

公开(公告)号：US09064719B1

公开(公告)日：2015-06-23

申请号：US14324090

申请日：2014-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L23/52 ,  H01L27/06 ,  H01L27/12

CPC classification number: H01L27/0688 ,  H01L27/0629 ,  H01L27/0682 ,  H01L27/1203 ,  H01L2224/48247

Abstract: An integrated circuit includes a capacitor and a non-inductive resistor. A substrate has a capacitor area and a resistor area. A patterned stacked structure including a bottom conductive layer, an insulating layer and a top conductive layer from bottom to top is sandwiched by a first dielectric layer and a second dielectric layer disposed on the substrate. A first metal plug and a second metal plug contact the top conductive layer and the bottom conductive layer of the capacitor area respectively, thereby the patterned stacked structure in the capacitor area constituting the capacitor. A third metal plug and a fourth metal plug contact the bottom conductive layer and the top conductive layer of the resistor area respectively, and a fifth metal plug contacts the bottom conductive layer and the top conductive layer of the resistor area simultaneously, thereby the patterned stacked structure in the resistor area constituting the non-inductive resistor.

Abstract translation: 集成电路包括电容器和非感性电阻器。 衬底具有电容器区域和电阻器区域。 包括底部导电层，绝缘层和从顶部到顶部的顶部导电层的图案化堆叠结构被设置在基板上的第一介电层和第二介电层夹在中间。 第一金属插塞和第二金属插头分别与电容器区域的顶部导电层和底部导电层接触，从而构成电容器区域中的图案化堆叠结构。 第三金属插塞和第四金属插头分别接触电阻器区域的底部导电层和顶部导电层，并且第五金属插头同时接触电阻器区域的底部导电层和顶部导电层，由此图案化堆叠 构成无感电阻器的电阻区域的结构。

公开(公告)号：US11011649B2

公开(公告)日：2021-05-18

申请号：US16027386

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chen-Bin Lin ,  Ding-Lung Chen ,  Chi-Fa Ku

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L21/426 ,  H01L27/12 ,  H01L29/49

Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

公开(公告)号：US20180331233A1

公开(公告)日：2018-11-15

申请号：US16027386

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chen-Bin Lin ,  Ding-Lung Chen ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L21/426 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/426 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/7869

Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

公开(公告)号：US09887293B2

公开(公告)日：2018-02-06

申请号：US15191542

申请日：2016-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Chen-Bin Lin ,  Sanpo Wang ,  Chung-Yuan Lee ,  Chi-Fa Ku

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L29/78609 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions are disposed on the oxide-semiconductor layer. The first dielectric layer covers on the oxide-semiconductor layer and source/drain regions. A second gate electrode is disposed between source/drain regions and partially covers the oxide-semiconductor layer. The oxide-semiconductor layer may be optionally disposed between the first gate electrode and the oxide-semiconductor layer or be disposed on the second gate electrode.

公开(公告)号：US20170338351A1

公开(公告)日：2017-11-23

申请号：US15191542

申请日：2016-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Ding-Lung Chen ,  Chen-Bin Lin ,  SANPO WANG ,  Chung-Yuan Lee ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/78609 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions are disposed on the oxide-semiconductor layer. The first dielectric layer covers on the oxide-semiconductor layer and source/drain regions. A second gate electrode is disposed between source/drain regions and partially covers the oxide-semiconductor layer. The oxide-semiconductor layer may be optionally disposed between the first gate electrode and the oxide-semiconductor layer or be disposed on the second gate electrode.

公开(公告)号：US20170110192A1

公开(公告)日：2017-04-20

申请号：US15382755

申请日：2016-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Chen-Bin Lin ,  Chi-Fa Ku ,  Shao-Hui Wu

IPC: G11C14/00 ,  H01L49/02 ,  H01L29/04 ,  H01L27/105 ,  H01L29/24 ,  H01L29/66 ,  H01L27/108

CPC classification number: G11C14/0009 ,  G11C14/0027 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L28/60

Abstract: A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared. At least a first dielectric layer is formed on the main surface of the semiconductor substrate. A first OS FET device and a second OS FET device are formed on the first dielectric layer. At least a second dielectric layer is formed to cover the first dielectric layer, the first OS FET device, and the second OS FET device. A first MIM capacitor and a second MIM capacitor are formed on the second dielectric layer. The first MIM capacitor is electrically coupled to the first OS FET device, thereby constituting a DOSRAM cell. The second MIM capacitor is electrically coupled to the second OS FET device, thereby constituting a NOSRAM cell.

公开(公告)号：US20170098599A1

公开(公告)日：2017-04-06

申请号：US14873189

申请日：2015-10-01

Applicant: United Microelectronics Corp.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L23/498 ,  H01L27/108 ,  H01L27/115 ,  H01L29/66 ,  H01L27/12 ,  H01L21/48 ,  H01L29/786

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5385 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1259 ,  H01L27/1262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. An interposer substrate is provided. At least one oxide semiconductor transistor is formed on the interposer substrate. At least one trough silicon via (TSV) is formed in the interposer substrate. An interconnection structure on the interposer substrate, and the at least one oxide semiconductor transistor is connected to the interconnection structure.