公开(公告)号：US09811344B2

公开(公告)日：2017-11-07

申请号：US15357145

申请日：2016-11-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F13/00 ,  G06F9/38 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F9/44 ,  G06F13/364 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0875 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  H04L9/08 ,  H01L21/66

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to generate a default core ID and to sample the indicator. When the indicator indicates a first predetermined value, the default core ID generated by a default one of the plurality of processing cores designates the default processing core to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to generate alternate core IDs that are different from the default core IDs. One of the alternate core IDs designates an alternate processing core, other than the default processing core, to be the bootstrap processor.

公开(公告)号：US09507404B2

公开(公告)日：2016-11-29

申请号：US14281621

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Stephan Gaskins

IPC: G06F1/00 ,  G06F1/32 ,  G06F12/08 ,  G06F13/24 ,  G06F9/38 ,  G06F9/30 ,  G06F9/44 ,  G06F1/04 ,  G06F1/12

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

Abstract translation: 微处理器包括多个核心，共享高速缓冲存储器和控制单元，其通过停止其时钟信号来单独地将每个核心置于睡眠状态。 每个核心执行睡眠指令，并且响应地使控制单元的相应请求将核心置于睡眠状态，控制单元响应地进行该操作，并且检测所有核心何时完成了各自的请求，并且响应地只唤醒最后请求的核心 。 最后一个内核写回并使共享高速缓存内存无效，并指示它已被无效，并向控制单元发出请求以使最后一个核心返回休眠状态。 控制单元将最后一个核心置于休眠状态，并持续保持其他内核处于睡眠状态，同时最后一个内核回写并使共享缓存内存无效，表示共享高速缓存内存无效，并返回睡眠状态。

公开(公告)号：US20150067214A1

公开(公告)日：2015-03-05

申请号：US14281621

申请日：2014-05-19

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Stephan Gaskins

IPC: G06F1/32 ,  G06F13/24 ,  G06F12/08

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

Abstract translation: 微处理器包括多个核心，共享高速缓冲存储器和控制单元，其通过停止其时钟信号来单独地将每个核心置于睡眠状态。 每个核心执行睡眠指令，并且响应地使控制单元的相应请求将核心置于睡眠状态，控制单元响应地进行该操作，并且检测所有核心何时完成了各自的请求，并且响应地只唤醒最后请求的核心 。 最后一个内核写回并使共享高速缓存内存无效，并指示它已被无效，并向控制单元发出请求以使最后一个核心返回休眠状态。 控制单元将最后一个核心置于休眠状态，并持续保持其他内核处于睡眠状态，同时最后一个内核回写并使共享缓存内存无效，表示共享高速缓存内存无效，并返回睡眠状态。

公开(公告)号：US10204056B2

公开(公告)日：2019-02-12

申请号：US14188905

申请日：2014-02-25

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F12/0891 ,  G06F12/0842 ,  G06F1/32 ,  G06F12/0864 ,  G06F12/0893 ,  G06F9/50

Abstract: A microprocessor includes a cache memory and a control module. The control module makes the cache size zero and subsequently make it between zero and a full size of the cache, counts a number of evictions from the cache after making the size between zero and full and increase the size when the number of evictions reaches a predetermined number of evictions. Alternatively, a microprocessor includes: multiple cores, each having a first cache memory; a second cache memory shared by the cores; and a control module. The control module puts all the cores to sleep and makes the second cache size zero and receives a command to wakeup one of the cores. The control module counts a number of evictions from the first cache of the awakened core after receiving the command and makes the second cache size non-zero when the number of evictions reaches a predetermined number of evictions.

公开(公告)号：US09792112B2

公开(公告)日：2017-10-17

申请号：US14281786

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F9/445 ,  G06F9/44 ,  G06F11/36 ,  G06F9/32 ,  G06F9/26

CPC classification number: G06F8/665 ,  G06F8/654 ,  G06F8/656 ,  G06F8/67 ,  G06F9/268 ,  G06F9/328 ,  G06F11/366 ,  Y02B60/183 ,  Y02D10/42

Abstract: A microprocessor includes a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode. A first core of the plurality of processing cores is configured to encounter an instruction that instructs the first core to apply a microcode patch. The first core of the plurality of processing cores is further configured to, in response to encountering the instruction, inform each core of the other of the plurality of processing cores of the microcode patch and apply the microcode patch to the hardware of the first core. Each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to the hardware of the core, in response to being informed by the first core.

公开(公告)号：US20150067307A1

公开(公告)日：2015-03-05

申请号：US14281796

申请日：2014-05-19

Applicant: Via Technologies, Inc.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F9/30

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction.

Abstract translation: 一种微处理器，多个处理核心，其中所述多个处理核心中的每一个都实例化相应的体系结构可视存储资源。 多个处理核心的第一核心被配置为遇到指令第一核心以由架构指令指定的值来更新第一核心的各个架构可见存储资源的架构指令。 第一核还被配置为响应于遇到结构指令而向多个处理核心中的另一个处理核心中的每一个提供该值，并用该值来更新第一核心的相应的架构可见存储资源。 除了第一核心之外的多个处理核心的每个核心被配置为利用由第一核心提供的值来更新核心的各个体系结构可见的存储资源，而不会遇到建筑指令。

公开(公告)号：US09575541B2

公开(公告)日：2017-02-21

申请号：US14281796

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F15/16 ,  G06F1/04 ,  G06F1/32 ,  G06F12/08 ,  G06F13/24 ,  G06F9/44 ,  G06F9/38 ,  G06F9/30 ,  G06F1/12

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction.

Abstract translation: 一种微处理器，多个处理核心，其中所述多个处理核心中的每一个都实例化相应的体系结构可视存储资源。 多个处理核心的第一核心被配置为遇到指令第一核心以由架构指令指定的值来更新第一核心的各个架构可见存储资源的架构指令。 第一核还被配置为响应于遇到结构指令而向多个处理核心中的另一个处理核心中的每一个提供该值，并用该值来更新第一核心的相应的架构可见存储资源。 除了第一核心之外的多个处理核心的每个核心被配置为利用由第一核心提供的值来更新核心的各个体系结构可见的存储资源，而不会遇到建筑指令。

公开(公告)号：US09367497B2

公开(公告)日：2016-06-14

申请号：US14522931

申请日：2014-10-24

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F13/36 ,  G06F15/163 ,  G06F1/32 ,  G06F1/24 ,  G06F9/30 ,  G06F9/50 ,  G06F9/445 ,  G06F15/82 ,  G06F11/36 ,  G06F11/14

CPC classification number: G06F1/26 ,  G06F1/24 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30083 ,  G06F9/44505 ,  G06F9/5094 ,  G06F11/1423 ,  G06F11/3664 ,  G06F13/36 ,  G06F15/163 ,  G06F15/82 ,  Y02D10/14 ,  Y02D10/22

Abstract: A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires, extrinsic to a system bus connected to a chipset, which facilitate non-system-bus inter-core communications. At least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of structuring sideband-based inter-core communications. The method includes determining an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core, and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated. Each core is configured to conditionally drive a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.

Abstract translation: 一种用于动态重新配置多核微处理器的一个或多个核心的方法，所述多核微处理器包括多个核心和边带通信线路，其外部连接到连接到芯片组的系统总线，这有助于非系统总线核心间通信。 为了构建基于边带的核心间通信的目的，至少一些核可操作以可重新配置地指定或不具有主凭证。 该方法包括确定微处理器的核心的初始配置，该配置指定至少一个核心，但不将所有核心指定为主核心，并且根据修改的配置重新配置核心，该修改的配置删除主命名 从最初如此指定的核心，并将主指定分配给最初未指定的核心。 每个核心被配置为基于其指定或不存在作为主核心有条件地驱动其所连接的边带通信线。

公开(公告)号：US20150067318A1

公开(公告)日：2015-03-05

申请号：US14281709

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F9/44

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate multiple of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate a single processing core of the plurality of processing cores to be the bootstrap processor.

Abstract translation: 微处理器包括指示器和多个处理核心。 多个处理核心中的每一个被配置为对指示器进行采样。 当指示符指示第一预定值时，多个处理核被配置为将多个处理核中的多个共同指定为自举处理器。 当指示符指示与第一预定值不同的第二预定值时，多个处理核被配置为将多个处理核中的单个处理核共同地指定为引导处理器。

公开(公告)号：US20150067306A1

公开(公告)日：2015-03-05

申请号：US14281551

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Stephan Gaskins

IPC: G06F9/30

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the plurality of processing cores. Each core of the plurality of processing cores comprises microcode run by the core that implements architectural instructions of an instruction set architecture of the microprocessor. The microcode is configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores.

Abstract translation: 微处理器包括多个处理核心和由多个处理核心中的每一个可读和写的非随机存取存储器（RAM）。 多个处理核心的每个核心包括实现微处理器的指令集架构的架构指令的由核心运行的微代码。 微码被配置为读取和写入非空白RAM以实现多个处理核之间的核心间通信。