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    Method of fabricating a semiconductor device
    12.
    发明授权
    Method of fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07960290B2

    公开(公告)日：2011-06-14

    申请号：US11799637

    申请日：2007-05-02

    申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

    发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

    IPC分类号： H01L23/522

    CPC分类号： H01L23/5222 ,  H01L21/76224 ,  H01L21/7682 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating a semiconductor device. A preferred embodiment comprises forming a via in a semiconductor substrate, filling the via with a disposable material such as amorphous carbon, forming a dielectric layer on the substrate covering the via, performing a back side etch to expose the disposable material in the via. A back side dielectric layer is then depositing, covering the exposed via. A small opening is then formed, and the disposable material is removed, for example by an isotropic etch process. The via may now be filled with a metal and used as a conductor or a dielectric material. The via may also be left unfilled to be used as an air gap.

    摘要翻译： 一种半导体器件的制造方法。 优选实施例包括在半导体衬底中形成通孔，用诸如无定形碳的一次性材料填充通孔，在覆盖通孔的衬底上形成电介质层，进行背面蚀刻以暴露通孔中的一次性材料。 然后沉积背面电介质层，覆盖暴露的通孔。 然后形成小的开口，并且例如通过各向同性蚀刻工艺去除一次性材料。 通孔现在可以填充金属并用作导体或电介质材料。 通孔也可以不填充以用作气隙。

    Formation of through via before contact processing
    13.
    发明授权
    Formation of through via before contact processing 有权
    在联系处理之前形成通孔

    公开(公告)号：US07939941B2

    公开(公告)日：2011-05-10

    申请号：US11769559

    申请日：2007-06-27

    申请人： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu

    发明人： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

    摘要： The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.

    摘要翻译： 描述了在集成电路（IC）管芯或晶片中形成通孔硅通孔（TSV），其中在接触或金属化处理之前的集成工艺中形成TSV。 然后可以在TSV已经就位之后制造触点和接合焊盘，这允许TSV更致密并且允许TSV设计中的更多自由度。 通过在TSV和接合焊盘之间提供更密集的连接，单个晶片和管芯可以直接接合在接合焊盘处。 因此，导电接合材料通过接合焊盘保持与TSV和其它IC部件的电连接。

    Through-Silicon Via Sidewall Isolation Structure
    15.
    发明申请
    Through-Silicon Via Sidewall Isolation Structure 审中-公开
    通过硅片通过侧壁隔离结构

    公开(公告)号：US20100187694A1

    公开(公告)日：2010-07-29

    申请号：US12617494

    申请日：2009-11-12

    申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

    发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/76898 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/05552

    摘要： A system and method for an improved through-silicon via isolation structure is provided. An embodiment comprises a semiconductor device having a substrate with electrical circuitry formed thereon. One or more dielectric layers are formed over the substrate, and an opening is etched into the structure extending from a surface of the one or more dielectric layers through the one or more dielectric layers into the substrate; the opening having sidewalls. A low-K dielectric layer is formed over the sidewalls of the opening. The opening is filled with a conductive material and/or a barrier layer creating a through-silicon via that is isolated from the surrounding substrate by the low-K dielectric layer.

    摘要翻译： 提供了一种用于改进的通硅隔离结构的系统和方法。 实施例包括具有在其上形成有电路的基板的半导体器件。 在衬底上形成一个或多个电介质层，并且将开口蚀刻到从一个或多个电介质层的表面延伸通过一个或多个电介质层到衬底中的结构中; 该开口具有侧壁。 在开口的侧壁上形成低K电介质层。 开口填充有导电材料和/或阻挡层，其产生通过低K电介质层与周围基底隔离的穿硅通孔。

    Method of fabricating a semiconductor device
    16.
    发明申请
    Method of fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20080272498A1

    公开(公告)日：2008-11-06

    申请号：US11799637

    申请日：2007-05-02

    申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

    发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

    IPC分类号： H01L23/522 ,  H01L21/302 ,  H01L21/4763

    CPC分类号： H01L23/5222 ,  H01L21/76224 ,  H01L21/7682 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating a semiconductor device. A preferred embodiment comprises forming a via in a semiconductor substrate, filling the via with a disposable material such as amorphous carbon, forming a dielectric layer on the substrate covering the via, performing a back side etch to expose the disposable material in the via. A back side dielectric layer is then depositing, covering the exposed via. A small opening is then formed, and the disposable material is removed, for example by an isotropic etch process. The via may now be filled with a metal and used as a conductor or a dielectric material. The via may also be left unfilled to be used as an air gap.

    摘要翻译： 一种半导体器件的制造方法。 优选实施例包括在半导体衬底中形成通孔，用诸如无定形碳的一次性材料填充通孔，在覆盖通孔的衬底上形成电介质层，进行背面蚀刻以暴露通孔中的一次性材料。 然后沉积背面电介质层，覆盖暴露的通孔。 然后形成小的开口，并且例如通过各向同性蚀刻工艺去除一次性材料。 通孔现在可以填充金属并用作导体或介电材料。 通孔也可以不填充以用作气隙。