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    Semiconductor device having protective and test circuits
    12.
    发明授权
    Semiconductor device having protective and test circuits 失效
    具有保护和测试电路的半导体器件

    公开(公告)号：US06442009B1

    公开(公告)日：2002-08-27

    申请号：US09604720

    申请日：2000-06-28

    申请人： Yasushi Kameda ,  Makoto Segawa

    发明人： Yasushi Kameda ,  Makoto Segawa

    IPC分类号： H02H900

    CPC分类号： G11C29/50 ,  H02H9/046

    摘要： A semiconductor device has an internal circuit (2), a PAD, a NMOS Tr (QN) as a protective transistor formed between a node (N) on a signal line and a first power source (Vss), and a NOR gate (G1) as a logical gate connected to a gate as a control terminal of the NMOS transistor (QN). The internal circuit (2) is connected to the PAD through the signal line. The NOR gate (G1) keeps the protective transistor (QN) an OFF state during a normal operation of the internal circuit (2). In addition, the semiconductor device further includes a test circuit (21). The output from the NOR gate (G1), whose one input is the output from the test circuit (21), is supplied to the gate of the NMOS transistor (QN). The output from the test circuit (21) is thereby output to outside through the NMOS transistor (QN) and the PAD.

    摘要翻译： 半导体器件具有形成在信号线上的节点（N）和第一电源（Vss）之间的作为保护晶体管的内部电路（2），PAD，NMOS Tr（QN）以及NOR门（G1） ）作为连接到作为NMOS晶体管（QN）的控制端的栅极的逻辑栅极。 内部电路（2）通过信号线连接到PAD。 NOR门（G1）在内部电路（2）的正常工作期间保持保护晶体管（QN）为OFF状态。 另外，半导体器件还包括测试电路（21）。 来自测试电路（21）的输出端的NOR门（G1）的输出被提供给NMOS晶体管（QN）的栅极。 因此，测试电路（21）的输出通过NMOS晶体管（QN）和PAD输出到外部。

    Detector circuit for testing semiconductor memory device
    13.
    发明授权
    Detector circuit for testing semiconductor memory device 失效
    用于测试半导体存储器件的检测电路

    公开(公告)号：US5400282A

    公开(公告)日：1995-03-21

    申请号：US914744

    申请日：1992-07-17

    申请人： Youichi Suzuki ,  Makoto Segawa ,  Toshiaki Ohno ,  Sumako Shiraishi

    发明人： Youichi Suzuki ,  Makoto Segawa ,  Toshiaki Ohno ,  Sumako Shiraishi

    IPC分类号： G11C29/00 ,  G01R31/28 ,  G11C11/413 ,  G11C29/06 ,  G11C29/34

    CPC分类号： G11C29/34

    摘要： A semiconductor memory device having a normal mode of reading and writing data from and to a selected memory cell of a memory cell array. The semiconductor memory device is characterized by control means for switching the normal operation mode to a test mode in response to a test mode signal applied to a certain input terminal, selecting all desired memory cells of the memory cell array at a time, and allowing data applied to a data input terminal to be written to all the selected and desired memory cells at one time.

    摘要翻译： 具有从存储单元阵列的选定存储单元读取数据的正常模式的半导体存储器件。 半导体存储器件的特征在于用于响应于施加到某个输入端子的测试模式信号将正常操作模式切换到测试模式的控制装置，一次选择存储单元阵列的所有期望存储单元，并允许数据 一次应用于要写入所有所选存储单元的数据输入端。

    Semiconductor integrated circuit device
    14.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路设备

    公开(公告)号：US5079612A

    公开(公告)日：1992-01-07

    申请号：US564615

    申请日：1990-08-09

    申请人： Hiroshi Takamoto ,  Makoto Segawa

    发明人： Hiroshi Takamoto ,  Makoto Segawa

    IPC分类号： H01L21/822 ,  H01L27/02 ,  H01L27/04

    CPC分类号： H01L27/0248

    摘要： A semiconductor IC device including a main circuit block and at least one subcircuit block, each having a ground terminal, a supply voltage terminal and an input or output terminal. A first ground line is connected to the ground terminal of the main circuit block and arranged within a wiring domain of the main circuit block and adjacent to the subcircuit blocks. A second ground line is connected to the ground terminal of the subcircuit block and arranged within a wiring domain of the subcircuit block and adjacent to the main circuit block. Protective elements are connected between the first and second ground lines so as to form short circuits through at least one of the first and second ground lines. In the IC device thus configured, all of the input and output terminals resist overvoltage, in every case where any one of the ground terminals and the supply voltage terminals is determined as a reference potential terminal, without complicating the protective element wiring arrangement or increasing the chip area and the cost thereof.

    Semiconductor integrated circuit device
    16.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US4399520A

    公开(公告)日：1983-08-16

    申请号：US235859

    申请日：1981-02-19

    申请人： Shoji Ariizumi ,  Makoto Segawa ,  Hisaaki Maiwa ,  Seishi Okamoto

    发明人： Shoji Ariizumi ,  Makoto Segawa ,  Hisaaki Maiwa ,  Seishi Okamoto

    IPC分类号： G11C11/403 ,  G11C11/412 ,  G11C19/18 ,  H01L27/105 ,  G11C7/00

    CPC分类号： H01L27/105 ,  G11C11/403 ,  G11C11/412 ,  G11C19/18

    摘要： A semiconductor integrated circuit having a memory and an adjacent peripheral circuit generating minority carriers which can destroy data in a portion of the memory at low temperatures. The load resistance in the portion is made lower or the storage capacity is made higher in the portion than in the remainder of the memory so that at low temperatures data is not lost and the energy consumption of the circuit is not unduly increased.

    摘要翻译： 具有存储器和相邻外围电路的半导体集成电路产生少量载流子，这些载流子可以在低温下破坏存储器的一部分中的数据。 部分中的负载电阻降低或存储容量在存储器的剩余部分中比存储容量高，使得在低温下数据不会丢失，并且电路的能量消耗不会不适当地增加。

    Semiconductor memory device implemented with a test circuit
    19.
    发明授权
    Semiconductor memory device implemented with a test circuit 失效
    用测试电路实现的半导体存储器件

    公开(公告)号：US06529438B1

    公开(公告)日：2003-03-04

    申请号：US09722195

    申请日：2000-11-22

    申请人： Yoichi Suzuki ,  Akihiro Mishima ,  Mitsuhiko Kosakai ,  Makoto Segawa ,  Yasuo Naruke

    发明人： Yoichi Suzuki ,  Akihiro Mishima ,  Mitsuhiko Kosakai ,  Makoto Segawa ,  Yasuo Naruke

    IPC分类号： G11C800

    CPC分类号： G11C8/10 ,  G11C29/02

    摘要： An improved semiconductor memory device capable of easily detecting the location of a defective bit line and a defective memory cell as a leakage current path for a short time is provided. A region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first large region and a remaining second large region, either of said first and second large regions being selected by simultaneously selecting a predetermined number of said column selection lines. Then, a region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first small region and a remaining second small region, said first and second small regions constituting said one of the first and second large regions, either of said first and second small regions being selected by simultaneously selecting a predetermined number of said column selection lines. For this purpose, an address signal output control circuit is provided within the semiconductor memory device. The address signal output control circuit is supplied with an address output control signal as externally given as a control signal for the purpose of selecting said row selection line by taking control of said row addressing signal in order to perform the control process as described above.

    摘要翻译： 提供一种改进的半导体存储器件，其能够容易地将缺陷位线和缺陷存储器单元的位置检测为短时间的漏电流路径。 通过检测第一大区域和剩余第二大区域中的一个来确定流过不小于预定值的漏电流的区域，通过同时选择预定数量的所述列选择线来选择所述第一和第二大区域中的任一个 。 然后，通过检测构成第一和第二大区域中的一个的第一和第二小区域的第一小区域和第二小区域中的一个来确定流过不小于预定值的漏电流的区域， 通过同时选择预定数量的所述列选择线来选择所述第一和第二小区域。 为此，在半导体存储器件内提供地址信号输出控制电路。 为了通过控制所述行寻址信号来选择所述行选择线，为了执行如上所述的控制处理，地址信号输出控制电路被提供作为外部给定的地址输出控制信号作为控制信号。

    Semiconductor memory device for use in apparatus requiring high-speed access to memory cells
    20.
    再颁专利
    Semiconductor memory device for use in apparatus requiring high-speed access to memory cells 失效
    用于需要高速存取存储器单元的设备中的半导体存储器件

    公开(公告)号：USRE36404E

    公开(公告)日：1999-11-23

    申请号：US970780

    申请日：1997-11-14

    申请人： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

    发明人： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

    IPC分类号： G11C11/41 ,  G11C8/14 ,  G11C11/40 ,  G11C7/00

    CPC分类号： G11C8/14

    摘要： A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.

    摘要翻译： 一种半导体存储器件，包括多个单元阵列部分，每个单元阵列部分具有以矩阵形式设置的多个存储单元，所述多个单元阵列部分在行方向上并置。 主字线各自为每行中的所有多个单元阵列部分共同设置，行选择信号被应用于每个主字线。 部分字线连接到每行的每个单元阵列部分中的存储单元，用于激活存储单元。 为每个单元阵列区段提供区段选择线，区段选择信号被应用于每个区段选择线。 为每个单元阵列部提供逻辑电路，每个逻辑电路连接到每个主字线和选区线，执行行选择信号和区段选择信号之间的逻辑运算，并且当逻辑 运算结果满足规定的逻辑条件。 每个逻辑电路包括第一反相器，CMOS型第二反相器和N沟道晶体管。 每个主字线连接到第一和第二逆变器的输入端。 各段选择线连接到N型晶体管的漏极和第二反相器的P沟道晶体管的源极。 N沟道晶体管的栅极连接到第一反相器的输出端子，并且每个部分字线连接到N沟道晶体管的源极和第二反相器的输出端子。 位线连接到每个存储器单元，用于从所选存储单元接收数据并输出数据。