公开(公告)号：US20110189820A1

公开(公告)日：2011-08-04

申请号：US12700217

申请日：2010-02-04

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L21/50

CPC分类号： H01L24/96 ,  H01L21/6836 ,  H01L23/3178 ,  H01L23/544 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/24101 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/25175 ,  H01L2224/2929 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/07802 ,  Y10S438/928 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： In a method of manufacturing a layered chip package, a layered substructure is fabricated and used to produce a plurality of layered chip packages. The layered substructure includes first to fourth substructures stacked, each of the substructures including an array of a plurality of preliminary layer portions. In the step of fabricating the layered substructure, initially fabricated are first to fourth pre-polishing substructures each having first and second surfaces. Next, the first and second pre-polishing substructures are bonded to each other with the first surfaces facing each other, and then the second surface of the second pre-polishing substructure is polished to form a first stack. Similarly, the third and fourth pre-polishing substructures are bonded to each other and the second surface of the third pre-polishing substructure is polished to form a second stack. Then, the first and second stacks are bonded to each other.

摘要翻译： 在制造层状芯片封装的方法中，制造层叠子结构并用于制造多个分层芯片封装。 分层子结构包括堆叠的第一至第四子结构，每个子结构包括多个预备层部分的阵列。 在制造层状子结构的步骤中，最初制造的是具有第一和第二表面的第一至第四预抛光子结构。 接下来，第一和第二预抛光子结构彼此接合，第一表面彼此面对，然后抛光第二预抛光子结构的第二表面以形成第一叠层。 类似地，第三和第四预抛光子结构彼此结合，并且抛光第三预抛光子结构的第二表面以形成第二堆叠。 然后，第一和第二堆叠彼此结合。

公开(公告)号：US20130100555A1

公开(公告)日：2013-04-25

申请号：US13279978

申请日：2011-10-24

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Shigeki TANEMURA ,  Kazuki SATO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Shigeki TANEMURA ,  Kazuki SATO ,  Atsushi IIJIMA

IPC分类号： G11B5/31 ,  G11B5/127 ,  G11B5/48

CPC分类号： G11B5/1278 ,  G11B5/3116 ,  G11B5/315 ,  G11B5/3163 ,  Y10T29/49023 ,  Y10T29/49032 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052

摘要： A thin-film magnetic head is constructed such that a main magnetic pole layer, a lower shield layer, an upper shield layer and a thin-film coil are laminated on a substrate. A method of manufacturing the thin-film magnetic head has a lower shield layer forming step. This step comprises a step of forming a first lower shield part in a lower shield planned area, including a planned line along the medium-opposing surface, a step of forming a partial lower seed layer having a partial arrangement structure in which the partial lower seed layer is arranged on a lower formation zone except a lower exception zone including the planned line, a step of forming a second lower shield part on the partial lower seed layer.

摘要翻译： 薄膜磁头被构造成使得主磁极层，下屏蔽层，上屏蔽层和薄膜线圈层叠在基板上。 制造薄膜磁头的方法具有较低的屏蔽层形成步骤。 该步骤包括在下屏蔽计划区域中形成第一下屏蔽部分的步骤，包括沿着中间相对表面的计划线，形成具有部分布置结构的部分下部种子层的步骤，其中部分下部种子 层布置在下形成区域，除了包括预定线的下异常区域，在部分下种子层上形成第二下屏蔽部分的步骤。

公开(公告)号：US20130020723A1

公开(公告)日：2013-01-24

申请号：US13184971

申请日：2011-07-18

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC分类号： H01L23/52

CPC分类号： H01L23/5389 ,  H01L21/6835 ,  H01L22/22 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/07802 ,  H01L2924/0105 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2224/27 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

摘要： A composite layered chip package includes a plurality of subpackages stacked on each other. Each subpackage includes a main body and wiring. The main body includes a main part including a plurality of layer portions, and further includes first terminals and second terminals that are disposed on top and bottom surfaces of the main part, respectively. The wiring is electrically connected to the first and second terminals. The number of the plurality of layer portions included in the main part is the same for all the plurality of subpackages, and the plurality of layer portions in every subpackage include at least one first-type layer portion. In each of at least two of the subpackages, the plurality of layer portions further include at least one second-type layer portion. The first-type layer portion includes a semiconductor chip connected to the wiring, whereas the second-type layer portion includes a semiconductor chip not connected to the wiring.

摘要翻译： 复合分层芯片封装包括彼此堆叠的多个子封装。 每个子包包括主体和接线。 主体包括包括多个层部分的主要部分，并且还包括分别设置在主要部分的顶表面和底表面上的第一端子和第二端子。 布线电连接到第一和第二端子。 包括在主要部分中的多个层部分的数量对于所有多个子包是相同的，并且每个子包中的多个层部分包括至少一个第一类型层部分。 在至少两个子包中的每一个中，多个层部分还包括至少一个第二类型层部分。 第一型层部分包括连接到布线的半导体芯片，而第二型层部分包括未连接到布线的半导体芯片。

公开(公告)号：US20120256321A1

公开(公告)日：2012-10-11

申请号：US13084053

申请日：2011-04-11

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC分类号： H01L23/48 ,  H01L21/50 ,  H01L21/78

CPC分类号： H01L21/561 ,  H01L23/3121 ,  H01L24/24 ,  H01L24/82 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/83005

摘要： A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes: a plurality of common electrodes electrically connected to the plurality of common lines; a plurality of non-contact electrodes that are electrically connected to the layer-dependent lines and are not in contact with the semiconductor chip in the layer portion; and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The layer-dependent lines are greater than the common lines in maximum width.

摘要翻译： 分层芯片封装包括主体和布线。 主体包括主要部分，其包括多个堆叠层部分，以及设置在主要部分的顶表面和底表面上的多个端子。 布线包括电连接到多个端子的多条线。 多条线包括多条公共线和多个依赖于层的线。 多个层部分中的每一个包括：电连接到多个公共线的多个公共电极; 多个非接触电极，其电连接到与层相关的线，并且不与层部分中的半导体芯片接触; 以及选择性连接电极，其仅选择性地电连接到所述层部分在多个层相关线中使用的与层相关的线。 层相关线大于最大宽度的公共线。

公开(公告)号：US20120025355A1

公开(公告)日：2012-02-02

申请号：US12848595

申请日：2010-08-02

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L23/544 ,  H01L21/00 ,  H01L23/552

CPC分类号： H01L23/552 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/83005 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01029 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/3025 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00

摘要： In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have electromagnetic shielding layer formed in regions other than the scribe-groove parts using a ferromagnetic body. Further, in the laminated semiconductor substrate, a through hole which penetrates the plurality of semiconductor substrates laminated in a laminated direction is formed in the scribe-groove part, and the laminated semiconductor substrate has a through electrode penetrating the plurality of semiconductor substrates through the through hole.

摘要翻译： 在层叠半导体衬底中层叠多个半导体衬底。 每个半导体衬底具有沿着划线形成的多个划线槽部分。 此外，每个半导体衬底具有彼此绝缘的多个器件区域，并且其中形成有半导体器件。 此外，最上面的基板和最下面的基板在使用铁磁体的划线槽部以外的区域中形成有电磁屏蔽层。 此外，在层叠半导体基板中，在划线槽部形成有贯穿层叠方向的多个半导体基板的贯通孔，并且层叠半导体基板具有穿过多个半导体基板的通孔， 孔。

公开(公告)号：US20110189822A1

公开(公告)日：2011-08-04

申请号：US12700297

申请日：2010-02-04

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L2224/16

摘要： A layered chip package includes a main body and wiring. The main body includes a plurality of layer portions stacked. The wiring is disposed on at least one side surface of the main body. In the method of manufacturing the layered chip package, first, a plurality of substructures each of which includes an array of a plurality of preliminary layer portions are used to fabricate a layered substructure that includes a plurality of pre-separation main bodies arranged in rows. Next, the layered substructure is cut into a plurality of blocks each of which includes a row of a plurality of pre-separation main bodies, and the wiring is formed on the plurality of pre-separation main bodies included in each block simultaneously. The plurality of pre-separation main bodies are then separated from each other. Each of the plurality of blocks includes a row of three, four, or five pre-separation main bodies.

摘要翻译： 分层芯片封装包括主体和布线。 主体包括堆叠的多个层部分。 布线布置在主体的至少一个侧表面上。 在制造层状芯片封装的方法中，首先，使用多个子结构，每个子结构包括多个预备层部分的阵列，以制造包括排成行的多个预分离主体的分层子结构。 接下来，将分层子结构切割成多个块，每个块包括一行多个预分离主体，并且布线同时形成在包括在每个块中的多个预分离主体上。 然后将多个预分离主体彼此分离。 多个块中的每个块包括一行三个，四个或五个预分离主体。

公开(公告)号：US20130075935A1

公开(公告)日：2013-03-28

申请号：US13240048

申请日：2011-09-22

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L23/52

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L24/06 ,  H01L24/24 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03011 ,  H01L2224/0346 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1064 ,  H01L2924/07802 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/0105

摘要： A composite layered chip package includes first and second subpackages that are stacked. Each subpackage includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface; first terminals disposed on the top surface of the main part; and second terminals disposed on the bottom surface of the main part. The first and second terminals are electrically connected to the wiring. The first and second subpackages are arranged in a specific relative positional relationship, different from a reference relative positional relationship, with each other.

摘要翻译： 复合分层芯片封装包括堆叠的第一和第二子封装。 每个子包包括主体和接线。 主体包括：具有顶表面和底表面的主要部分; 第一端子设置在主要部件的顶表面上; 以及设置在主要部分的底表面上的第二端子。 第一端子和第二端子电连接到布线。 第一子包和第二子包以不同于参考相对位置关系的特定相对位置关系彼此排列。

公开(公告)号：US20120313260A1

公开(公告)日：2012-12-13

申请号：US13156941

申请日：2011-06-09

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC分类号： H01L23/48 ,  H01L21/30

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/6835 ,  H01L22/22 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/0105 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/0231 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

摘要： A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

摘要翻译： 分层芯片封装包括主体和布线。 主体包括：具有顶表面和底表面并且包括彼此堆叠的三个或更多个层部分的主要部分; 多个第一端子，设置在所述主要部件的顶表面上; 以及设置在主要部分的底表面上的多个第二端子。 每个层部分包括具有第一和第二表面的半导体芯片和电连接到布线的多个电极。 多个电极设置在半导体芯片的第一表面的一侧。 位于最靠近主要部分的顶表面的第一层部分和最靠近主要部分的底表面的第二层部分被布置成使得它们各自的半导体芯片的第二表面朝向彼此。 多个第一端子通过使用第一层部分的多个电极形成。 多个第二端子通过使用第二层部分的多个电极形成。

公开(公告)号：US20120262825A1

公开(公告)日：2012-10-18

申请号：US13088852

申请日：2011-04-18

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Shigeki TANEMURA ,  Kazuki SATO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Shigeki TANEMURA ,  Kazuki SATO ,  Atsushi IIJIMA

IPC分类号： G11B5/17 ,  G11B5/127 ,  G11B5/48

CPC分类号： G11B5/1278 ,  G11B5/3146 ,  G11B5/3163 ,  G11B5/3967 ,  Y10T29/49032

摘要： A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, and a thin-film coil are laminated on a substrate. The write shield layer has an opposing shield part opposing the main magnetic pole layer and a front shield part. The front shield part is connected to the opposing shield part without straddling the thin-film coil. Besides, the front shield part has a shield front end face disposed in the medium-opposing surface and a shield upper end face formed distanced from the medium-opposing surface. Further, the front shield part has a shield connecting part. The shield front end face is connected to the shield upper end face by the shield connecting part.

摘要翻译： 薄膜磁头被构造为使得主磁极层，写入屏蔽层，间隙层和薄膜线圈层叠在基板上。 写屏蔽层具有与主磁极层相对的相对的屏蔽部分和前屏蔽部分。 前屏蔽部分连接到相对的屏蔽部分而不跨越薄膜线圈。 此外，前屏蔽部分具有设置在介质相对表面中的屏蔽前端面和远离介质相对表面形成的屏蔽上端面。 此外，前屏蔽部具有屏蔽连接部。 屏蔽前端面通过屏蔽连接部与屏蔽上端面连接。

公开(公告)号：US20120218663A1

公开(公告)日：2012-08-30

申请号：US13035234

申请日：2011-02-25

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Kazuki SATO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Kazuki SATO ,  Atsushi IIJIMA

IPC分类号： G11B5/10

CPC分类号： G11B5/1278 ,  G11B5/314 ,  G11B5/315 ,  G11B5/40 ,  G11B5/607 ,  G11B5/6076

摘要： A magnetic head includes a main pole, a write shield, a return path section, a heater that generates heat for making part of a medium facing surface protrude, and a sensor that detects contact of the part of the medium facing surface with a recording medium. The return path section includes: a yoke layer located backward of the main pole along the direction of travel of the recording medium; a first coupling part coupling the yoke layer and the write shield to each other; and a second coupling part located away from the medium facing surface and coupling the yoke layer and the main pole to each other. The first coupling part has an end face facing toward the yoke layer. This end face includes a middle portion spaced from the yoke layer and facing the yoke layer, and two side portions located on opposite sides of the middle portion in a track width direction and in contact with the yoke layer. The sensor is located between the middle portion and the yoke layer.

摘要翻译： 磁头包括主极，写屏蔽，返回路径部分，产生用于使介质面向表面的一部分突出的热量的加热器，以及传感器，其检测介质面向表面的一部分与记录介质的接触 。 返回路径部分包括：沿着记录介质的行进方向位于主极后方的轭层; 耦合所述轭层和所述写屏蔽的第一耦合部分; 以及第二联接部件，其远离所述介质面对表面并且将所述轭层和所述主极彼此耦合。 第一联接部分具有面向轭层的端面。 该端面包括与磁轭层间隔开并面对磁轭层的中间部分，以及位于轨道宽度方向上与中间部分相对侧并与磁轭层接触的两个侧部。 传感器位于中间部分和轭层之间。