公开(公告)号：US20110221070A1

公开(公告)日：2011-09-15

申请号：US13044457

申请日：2011-03-09

Applicant: Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L21/76805 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads.

公开(公告)号：US07781126B2

公开(公告)日：2010-08-24

申请号：US11223480

申请日：2005-09-08

Applicant: Yu-Lin Yen

Inventor： Yu-Lin Yen

IPC: G03F1/00

CPC classification number: G03F1/36 ,  G03F1/32

Abstract: The present invention provides a mask comprising a substrate, a plurality of strip patterns and at least an assist pattern. The strip patterns are disposed on the substrate and arranged in parallel to one another. The assist pattern is in a strip shape and disposed on the substrate. The assist pattern is arranged in parallel to and outside of the outermost strip pattern of the strip patterns. The assist pattern and the strip pattern have the same phase, while the assist pattern has a width larger than that of the strip patterns. When the mask is applied for exposure process, the pattern of the assist pattern will not be transferred to the underlying layer to be exposed.

Abstract translation: 本发明提供了一种掩模，其包括基底，多个条状图案和至少一个辅助图案。 带状图案设置在基板上并且彼此平行地布置。 辅助图案为带状，并设置在基板上。 辅助图案平行于带状图案的最外面带状图案并排布置。 辅助图案和带状图案具有相同的相位，而辅助图案的宽度大于带状图案的宽度。 当掩模用于曝光处理时，辅助图案的图案将不会转移到要暴露的下层。

公开(公告)号：US09136241B2

公开(公告)日：2015-09-15

申请号：US13446954

申请日：2012-04-13

Applicant: Yu-Lin Yen ,  Kuo-Hua Liu ,  Yu-Lung Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

Inventor： Yu-Lin Yen ,  Kuo-Hua Liu ,  Yu-Lung Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/04 ,  H01L21/50 ,  H01L23/00 ,  H01L23/10

CPC classification number: H01L24/29 ,  H01L23/10 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/29076 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83871 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.

Abstract translation: 本发明的实施例提供一种芯片封装的制造方法，包括：提供具有由多个划线分开的多个器件区域的半导体晶片; 将封装衬底接合到半导体晶片，其中间隔层设置在其间并限定分别暴露器件区域并且间隔层具有多个与半导体晶片的边缘相邻的通孔的空腔; 在通孔中填充粘合剂材料，其中间隔层的材料是粘合剂并且不同于粘合剂材料; 并且沿着划线切割半导体晶片，封装衬底和间隔层，以形成彼此分离的多个芯片封装。

公开(公告)号：US08624383B2

公开(公告)日：2014-01-07

申请号：US12836477

申请日：2010-07-14

Applicant: Yu-Lin Yen ,  Chen-Mei Fan

Inventor： Yu-Lin Yen ,  Chen-Mei Fan

IPC: H01L23/12

CPC classification number: H01L27/14618 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L27/14683 ,  H01L2224/0401 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/14

Abstract: The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device; a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.

Abstract translation: 本发明提供一种集成电路封装及其制造方法。 集成电路封装包括其上具有光敏器件的集成电路芯片; 焊盘，形成在集成电路芯片的上表面上并电连接到感光器件; 在焊盘和感光装置之间形成的屏障; 以及形成在集成电路芯片的侧壁上并电连接到接合焊盘的导电层。 阻挡层阻止粘合剂层溢出到形成有感光装置的区域中，以提高制造集成电路封装的成品率。

公开(公告)号：US08575634B2

公开(公告)日：2013-11-05

申请号：US12981600

申请日：2010-12-30

Applicant: Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

Inventor： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

IPC: H01L33/60 ,  H01L33/48

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a chip package, including: a chip having a semiconductor device thereon; a cap layer over the semiconductor device; a spacer layer between the chip and the cap layer, wherein the spacer layer surrounds the semiconductor device and forms a cavity between the chip and the cap layer; and an anti-reflective layer between the cap layer and the chip, wherein the anti-reflective layer has a overlapping region with the spacer layer and extends into the cavity. Furthermore, a method for fabricating a chip package is also provided.

Abstract translation: 本发明提供了一种芯片封装，包括：其上具有半导体器件的芯片; 半导体器件上的覆盖层; 在所述芯片和所述盖层之间的间隔层，其中所述间隔层围绕所述半导体器件并且在所述芯片和所述盖层之间形成空腔; 以及在所述盖层和所述芯片之间的抗反射层，其中所述抗反射层具有与所述间隔层的重叠区域并延伸到所述空腔中。 此外，还提供了一种用于制造芯片封装的方法。

公开(公告)号：US08003442B2

公开(公告)日：2011-08-23

申请号：US11878568

申请日：2007-07-25

Applicant: Yu-Lin Yen ,  Chen-Mei Fan

Inventor： Yu-Lin Yen ,  Chen-Mei Fan

IPC: H01L21/00

CPC classification number: H01L27/14618 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L27/14683 ,  H01L2224/0401 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/14

Abstract: The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device; a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.

Abstract translation: 本发明提供一种集成电路封装及其制造方法。 集成电路封装包括其上具有光敏器件的集成电路芯片; 焊盘，形成在集成电路芯片的上表面上并电连接到感光器件; 在焊盘和感光装置之间形成的屏障; 以及形成在集成电路芯片的侧壁上并电连接到接合焊盘的导电层。 阻挡层阻止粘合剂层溢出到形成有感光装置的区域中，以提高制造集成电路封装的成品率。

公开(公告)号：US20060094232A1

公开(公告)日：2006-05-04

申请号：US10976539

申请日：2004-10-29

Applicant: Chin-Ta Su ,  Jerry Lai ,  Yu-Lin Yen

Inventor： Chin-Ta Su ,  Jerry Lai ,  Yu-Lin Yen

IPC: H01L21/4763

CPC classification number: H01L21/76816 ,  H01L21/0276 ,  H01L21/32139 ,  H01L21/7685

Abstract: A method is provided for forming a semiconductor device that reduces metal-stress-induced photo misalignment by incorporating a multi-layered anti-reflective coating over a metal layer. The method includes providing a substrate with a conductive layer formed over the substrate, depositing a multi-layered anti-reflective coating (including alternating layers of titanium and titanium nitride), defining a plurality of conductive lines in connection with a first etching step, depositing a dielectric layer, and defining at least one via in connection with a second etching step.

Abstract translation: 提供了一种形成半导体器件的方法，该半导体器件通过在金属层上并入多层抗反射涂层来减少金属应力诱导的光失准。 该方法包括：在衬底上形成导电层的衬底，沉积多层抗反射涂层（包括钛和氮化钛的交替层），与第一蚀刻步骤相结合形成多条导电线，沉积 介电层，并且与第二蚀刻步骤相关地限定至少一个通孔。

公开(公告)号：US09559001B2

公开(公告)日：2017-01-31

申请号：US13024156

申请日：2011-02-09

Applicant: Yu-Lin Yen ,  Ming-Kun Yang ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Ming-Kun Yang ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763 ,  H01L23/58 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/05 ,  H01L2224/0501 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

Abstract: According to an embodiment of the invention, a chip package is provided, which includes: a substrate having an upper surface and a lower surface; a hole extending from the upper surface toward the lower surface; an insulating layer located overlying a sidewall of the hole; and a material layer located overlying the sidewall of the hole, wherein the material layer is separated from the upper surface of the substrate by a distance and a thickness of the material layer decreases along a direction toward the lower surface.

Abstract translation: 根据本发明的实施例，提供了一种芯片封装，其包括：具有上表面和下表面的基板; 从上表面向下表面延伸的孔; 位于所述孔的侧壁上方的绝缘层; 以及位于所述孔的侧壁上方的材料层，其中所述材料层与所述基板的上表面分离一定距离，并且所述材料层的厚度沿着朝向所述下表面的方向减小。

公开(公告)号：US08692382B2

公开(公告)日：2014-04-08

申请号：US13190388

申请日：2011-07-25

Applicant: Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/48

CPC classification number: H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/13025 ,  H01L2224/9202 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein an upper sidewall of the hole inclines to the lower surface of the substrate, and a lower sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

Abstract translation: 根据本发明的实施例，提供了芯片封装。 芯片封装包括：具有上表面和下表面的基板; 位于所述基板的下表面下方的多个导电垫; 位于导电垫之间的电介质层; 从衬底的上表面延伸到下表面的沟槽; 从所述沟槽的底部延伸到所述衬底的下表面的孔，其中所述孔的上侧壁倾斜到所述衬底的下表面，并且所述孔的下侧壁或底部暴露所述导电垫的一部分 ; 以及导电层，其位于所述孔中并电连接到至少一个所述导电焊盘。

公开(公告)号：US08552565B2

公开(公告)日：2013-10-08

申请号：US13204603

申请日：2011-08-05

Applicant: Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L21/76805 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located under the lower surface of the substrate, and a dielectric layer located between the conducting pads. A hole is provided in the substrate, which extends from the upper surface towards the lower surface of the substrate. A sidewall or a bottom of the hole exposes a portion of the conducting pads. The upper opening of the hole near the upper surface is smaller than a lower opening of the hole near the lower surface. An upper conducting pad has at least an opening or a trench exposing a lower conducting pad of the conducting pads. A conducting layer is disposed in the hole, which electrically contacting at least one of the conducting pads.

Abstract translation: 芯片封装包括具有上表面和下表面的衬底，位于衬底的下表面下方的多个导电衬垫以及位于导电焊盘之间的电介质层。 在衬底中设置有一个孔，该孔从衬底的上表面向下表面延伸。 孔的侧壁或底部暴露出导电垫的一部分。 上表面附近的孔的上部开口小于靠近下表面的孔的下部开口。 上导电焊盘至少具有暴露导电焊盘的下导电焊盘的开口或沟槽。 导电层设置在孔中，该导电层与至少一个导电垫电接触。