公开(公告)号：US09419127B2

公开(公告)日：2016-08-16

申请号：US14246675

申请日：2014-04-07

申请人： Rohm Co., Ltd.

发明人： Masaru Takaishi

IPC分类号： H01L29/78 ,  H01L29/866 ,  H01L29/872 ,  H01L27/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417

CPC分类号： H01L29/7808 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/7839 ,  H01L29/866 ,  H01L29/872

摘要： A semiconductor device includes switching devices in an epitaxial layer on a silicon substrate. Diffusion regions of different conductivity types are provided. In some instances, an electrode layer makes ohmic contact with the epitaxial layer and extends to, and makes ohmic contact with, a diffusion region electrically connected to the epitaxial layer. In some instances, diffusion regions of different conductivity types are arranged alternately one by one outward away from the epitaxial layer side.

摘要翻译： 半导体器件包括在硅衬底上的外延层中的开关器件。 提供不同导电类型的扩散区域。 在一些情况下，电极层与外延层进行欧姆接触并延伸到与外延层电连接的扩散区并使其与欧姆接触。 在一些情况下，不同导电类型的扩散区域在外延层外侧交替排列。

公开(公告)号：US09252264B2

公开(公告)日：2016-02-02

申请号：US14566294

申请日：2014-12-10

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Madhur Bobde ,  Hamza Yilmaz ,  Sik Lui ,  Daniel Ng

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L27/04 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L27/02 ,  H01L29/40 ,  H01L29/47 ,  H01L21/225 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45

CPC分类号： H01L29/7813 ,  H01L21/2257 ,  H01L27/0251 ,  H01L27/04 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7808 ,  H01L29/7811

摘要： Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

公开(公告)号：US20150380484A1

公开(公告)日：2015-12-31

申请号：US14845386

申请日：2015-09-04

申请人： ROHM CO., LTD.

发明人： Kenichi YOSHIMOCHI

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L21/76237 ,  H01L21/76205 ,  H01L21/763 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0664 ,  H01L27/11896 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66106 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/866 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/039 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/4911 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/03 ,  H01L2924/01029 ,  H01L21/78 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

摘要翻译： 半导体器件包括：第一导电型半导体层，包括其中形成有杂质区的晶体管的有源区和围绕有源区的边缘区;形成在有源区和边界之间的第二导电型沟道层; 形成半导体层的前表面，形成在有源区中的至少一个栅极沟槽，以从半导体层的前表面延伸通过沟道层，形成在栅极沟槽的内表面上的栅极绝缘膜， 形成在栅极沟槽中的栅极绝缘膜内部的栅极电极，以及布置在有源区域和边缘区域之间的至少一个隔离沟槽，以围绕有源区域并且从半导体层的前表面延伸穿过沟道层， 隔离沟槽的深度等于栅极沟槽的深度。

公开(公告)号：US09166037B2

公开(公告)日：2015-10-20

申请号：US13101155

申请日：2011-05-05

申请人： Wei-Chieh Lin

发明人： Wei-Chieh Lin

IPC分类号： H01L27/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L29/7813 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808

摘要： A power semiconductor device with an electrostatic discharge (ESD) structure includes an N-type semiconductor substrate, at least one ESD device, and at least one trench type transistor device. The N-type semiconductor has at least two trenches, and the ESD device is disposed in the N-type semiconductor substrate between the trenches. The ESD device includes a P-type first doped region, and an N-type second doped region and an N-type third doped region disposed in the P-type first doped region. The N-type second doped region is electrically connected to a gate of the trench type transistor device, and the N-type third doped region is electrically connected to a drain of the trench type transistor device.

摘要翻译： 具有静电放电（ESD）结构的功率半导体器件包括N型半导体衬底，至少一个ESD器件和至少一个沟槽型晶体管器件。 N型半导体具有至少两个沟槽，并且ESD器件设置在沟槽之间的N型半导体衬底中。 ESD器件包括P型第一掺杂区域和设置在P型第一掺杂区域中的N型第二掺杂区域和N型第三掺杂区域。 N型第二掺杂区域电连接到沟槽型晶体管器件的栅极，并且N型第三掺杂区域电连接到沟槽型晶体管器件的漏极。

公开(公告)号：US09105494B2

公开(公告)日：2015-08-11

申请号：US13776523

申请日：2013-02-25

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Yeeheng Lee ,  Madhur Bodbe ,  Daniel Calafut ,  Hamza Yilmaz ,  Xiaobin Wang ,  Ji Pan ,  Hong Chang ,  Jongoh Kim

IPC分类号： H01L21/82 ,  H01L27/088

CPC分类号： H01L29/66143 ,  H01L21/265 ,  H01L21/308 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/095 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66257 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/872

摘要： Aspects of the present disclosure describe a termination structure for a power MOSFET device. A termination trench may be formed into a semiconductor material and may encircle an active area of the MOSFET. The termination trench may comprise a first and second portion of conductive material. The first and second portions of conductive material are electrically isolated from each other. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开的方面描述了功率MOSFET器件的端接结构。 终端沟槽可以形成为半导体材料并且可以环绕MOSFET的有效区域。 端接沟槽可以包括导电材料的第一和第二部分。 导电材料的第一和第二部分彼此电绝缘。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20150084117A1

公开(公告)日：2015-03-26

申请号：US14037205

申请日：2013-09-25

申请人： Madhur Bobde

发明人： Madhur Bobde

IPC分类号： H01L29/78 ,  H01L29/70 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L21/8249 ,  H01L27/0716 ,  H01L29/66234 ,  H01L29/6628 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/70 ,  H01L29/732 ,  H01L29/7327 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/781 ,  H01L29/7813

摘要： A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal.

摘要翻译： 一种支撑在支撑外延层以形成底部源极金属氧化物半导体场效应晶体管（BS-MOSFET）的半导体衬底上的低电压瞬态电压抑制（TVS）器件，其包括被包围在体内的漏极区域包围的沟槽栅极 区域设置在半导体衬底的顶表面附近。 漏区与构成结二极管的体区接合。 外延层顶部的漏极区域构成双极晶体管，其顶部电极设置在用作漏极/集电极端子的半导体的顶表面上，而底部电极设置在用作源极/集电极端子的半导体衬底的底表面上， 发射电极。 主体区域还包括电连接到主体到源短路连接的表面体接触区域，从而将身体区域连接到用作源极/发射极端子的底部电极。

公开(公告)号：US20150001579A1

公开(公告)日：2015-01-01

申请号：US14485554

申请日：2014-09-12

申请人： FUJI ELECTRIC CO., LTD.

发明人： Takeyoshi NISHIMURA

IPC分类号： H01L27/02 ,  H01L29/866 ,  H01L29/78 ,  H01L29/739 ,  H01L27/06 ,  H01L29/66

CPC分类号： H01L27/0255 ,  H01L27/0629 ,  H01L28/60 ,  H01L29/0696 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/866 ,  H01L29/94

摘要： A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode.

摘要翻译： 电容分量区形成在温度检测二极管的下方或保护二极管的下方。 此外，电容分量区域形成在连接温度检测二极管和阳极电极焊盘的阳极金属布线下方以及连接温度检测二极管和阴极电极焊盘的阴极金属布线的下方。 电容分量区域是介于多晶硅层之间的绝缘膜。 具体地，在半导体衬底的第一主表面上依次形成第一绝缘膜，多晶硅导电层和第二绝缘膜，并且温度检测二极管，保护二极管，阳极金属布线或阴极金属 布线在第二绝缘膜的上表面上形成。 因此，可以提高温度检测二极管或保护二极管的静电电阻。

公开(公告)号：US20140339630A1

公开(公告)日：2014-11-20

申请号：US14329806

申请日：2014-07-11

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hamza Yilmaz ,  Madhur Bobde ,  Hong Chang ,  Yeeheng Lee ,  Daniel Calafut ,  Jongoh Kim ,  Sik Lui ,  John Chen

IPC分类号： H01L29/78 ,  H01L29/423

CPC分类号： H01L29/7813 ,  H01L27/0251 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7827

摘要： Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers that are formed along the sidewall of the gate caps. Additionally, the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The two-step gate oxide combined with the self-aligned source contacts allow for the production of devices with a pitch in the deep sub-micron level. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开的方面描述了具有自对准源触点的高密度沟槽基功率MOSFET和用于制造这种器件的方法。 源触点与沿着栅极盖的侧壁形成的间隔物自对准。 另外，有源器件可以具有两步栅极氧化物。 下部可以具有比栅极氧化物的上部的厚度大的厚度。 与自对准源触点结合的两步栅极氧化物允许生产具有深亚微米级的间距的器件。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US08878343B2

公开(公告)日：2014-11-04

申请号：US13849825

申请日：2013-03-25

申请人： Infineon Technologies Austria AG

发明人： Franz Hirler ,  Anton Mauder ,  Frank Pfirsch ,  Hans-Joachim Schulze

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/417 ,  H01L29/06 ,  H01L29/45 ,  H01L29/49

CPC分类号： H01L29/66143 ,  H01L21/823487 ,  H01L29/0626 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/6609 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7813

摘要： A field effect semiconductor device includes a semiconductor body having a main horizontal surface and a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type arranged between the first semiconductor region and the main horizontal surface, an insulating layer arranged on the main horizontal surface, and a first metallization arranged on the insulating layer. The first and second semiconductor regions form a pn-junction. The semiconductor body further has a deep trench extending from the main horizontal surface vertically below the pn-junction and including a conductive region insulated from the first semiconductor region and the second semiconductor region, and a narrow trench including a polycrystalline semiconductor region extending from the first metallization, through the insulating layer and at least to the conductive region. A vertical poly-diode structure including a horizontally extending pn-junction is arranged at least partly in the narrow trench.

摘要翻译： 场效应半导体器件包括具有主水平表面和第一导电类型的第一半导体区域的半导体本体，布置在第一半导体区域和主水平表面之间的第二导电类型的第二半导体区域，布置成 在主水平表面上，以及布置在绝缘层上的第一金属化。 第一和第二半导体区域形成pn结。 半导体本体还具有从垂直于pn结的下方的主水平表面延伸的深沟槽，并且包括与第一半导体区域和第二半导体区域绝缘​​的导电区域，以及包括从第一半导体区域延伸的多晶半导体区域的窄沟槽 通过绝缘层和至少导电区域进行金属化。 包括水平延伸的pn结的垂直多极二极管结构至少部分地布置在窄沟槽中。

公开(公告)号：US20140239388A1

公开(公告)日：2014-08-28

申请号：US13776523

申请日：2013-02-25

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Yeeheng Lee ,  Madhur Bobde ,  Daniel Calafut ,  Hamza Yilmaz ,  Xiaobin Wang ,  Ji Pan ,  Hong Chang ,  Jongoh Kim

IPC分类号： H01L27/088 ,  H01L21/82

CPC分类号： H01L29/66143 ,  H01L21/265 ,  H01L21/308 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/095 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66257 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/872

摘要： Aspects of the present disclosure describe a termination structure for a power MOSFET device. A termination trench may be formed into a semiconductor material and may encircle an active area of the MOSFET. The termination trench may comprise a first and second portion of conductive material. The first and second portions of conductive material are electrically isolated from each other. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本发明的方面描述了功率MOSFET器件的端接结构。 终端沟槽可以形成为半导体材料并且可以环绕MOSFET的有效区域。 端接沟槽可以包括导电材料的第一和第二部分。 导电材料的第一和第二部分彼此电绝缘。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。