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公开(公告)号:US20180217117A1
公开(公告)日:2018-08-02
申请号:US15920455
申请日:2018-03-14
申请人: Bao Tran
发明人: Bao Tran
CPC分类号: G01N33/0034 , B82Y10/00 , B82Y15/00 , B82Y40/00 , G01N27/122 , G01N27/128 , G01N27/4146 , G01N27/4148 , G11B9/14 , G11C11/21 , G11C11/54 , G11C13/0023 , G11C13/004 , G11C13/02 , G11C13/04 , H01L27/2463 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/16 , H01L51/4226 , H01L51/4253 , Y02E10/549 , Y10S977/762 , Y10S977/775 , Y10S977/938 , Y10S977/957
摘要: A device includes an upper metallic layer, a lower layer, and a nano sensor array positioned between the upper and lower layers to detect a presence of a gas, a chemical, or a biological object, wherein each sensor's electrical characteristic changes when encountering the gas, chemical or biological object.
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公开(公告)号:US10038139B2
公开(公告)日:2018-07-31
申请号:US15144639
申请日:2016-05-02
发明人: Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chin-Chieh Yang , Chih-Yang Chang , Yu-Wen Liao
CPC分类号: H01L45/1246 , H01L27/2436 , H01L45/04 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/124 , H01L45/1266 , H01L45/146 , H01L45/16 , H01L45/1675
摘要: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.
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公开(公告)号:US20180190717A1
公开(公告)日:2018-07-05
申请号:US15653181
申请日:2017-07-18
发明人: Shigeru Sugioka
CPC分类号: H01L27/2472 , G11C11/161 , G11C11/1673 , G11C11/1675 , H01L27/228 , H01L27/2436 , H01L43/12 , H01L45/06 , H01L45/085 , H01L45/1253 , H01L45/16 , H01L45/1666
摘要: Memory devices include an array of memory cells including magnetic tunnel junction regions. The array of memory cells includes access lines extending in a first direction and data lines extending in a second direction transverse to the first direction. A common source electrically couples memory cells of the array in both the first direction and the second direction. Electronic systems include such a memory device electrically coupled to a processor, to which at least one input device and at least one output device is electrically coupled. Methods of forming such an array of memory cells including a common source.
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公开(公告)号:US10014468B2
公开(公告)日:2018-07-03
申请号:US15499212
申请日:2017-04-27
申请人: ARM Ltd.
CPC分类号: H01L45/146 , G11C13/0007 , G11C2213/51 , H01L45/04 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/147 , H01L45/16
摘要: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to one or more barrier layers having various characteristics formed under and/or over and/or around correlated electron material.
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公开(公告)号:US10008668B2
公开(公告)日:2018-06-26
申请号:US15607095
申请日:2017-05-26
发明人: Mattia Boniardi , Andrea Redaelli
CPC分类号: H01L45/1293 , H01L27/2427 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/141 , H01L45/144 , H01L45/16 , H01L45/1608
摘要: A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.
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公开(公告)号:US20180175110A1
公开(公告)日:2018-06-21
申请号:US15884827
申请日:2018-01-31
发明人: Wen-Hsin Hsu , Ko-Chi Chen , Tzu-Yun Chang
IPC分类号: H01L27/24 , H01L45/00 , H01L23/528
CPC分类号: H01L27/2463 , H01L23/528 , H01L27/2436 , H01L45/08 , H01L45/1226 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1608 , H05K999/99
摘要: A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.
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公开(公告)号:US20180175022A1
公开(公告)日:2018-06-21
申请号:US15897524
申请日:2018-02-15
申请人: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
发明人: Olivier Weber , Emmanuel Richard , Philippe Boivin
IPC分类号: H01L27/06 , H01L27/24 , H01L21/84 , H01L29/732 , H01L45/00 , H01L21/8249
CPC分类号: H01L27/0623 , H01L21/8249 , H01L21/84 , H01L27/1207 , H01L27/2445 , H01L29/0813 , H01L29/41708 , H01L29/66303 , H01L29/732 , H01L45/06 , H01L45/1206 , H01L45/1233 , H01L45/126 , H01L45/16
摘要: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.
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18.
公开(公告)号:US10002906B2
公开(公告)日:2018-06-19
申请号:US15365143
申请日:2016-11-30
发明人: Francesco La Rosa , Stephan Niel , Arnaud Regnier
CPC分类号: H01L27/2409 , H01L27/1203 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/16
摘要: The array of diodes comprises a matrix plane of diodes arranged according to columns in a first direction and according to rows in a second direction orthogonal to the first direction. The said diodes comprise a cathode region of a first type of conductivity and an anode region of a second type of conductivity, the said cathode and anode regions being superposed and disposed on an insulating layer situated on top of a semiconductor substrate.
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19.
公开(公告)号:US20180158873A1
公开(公告)日:2018-06-07
申请号:US15367791
申请日:2016-12-02
发明人: Michiaki SANO , Zhen CHEN , Tetsuya YAMADA , Akira NAKADA , Yasuke ODA , Manabu HAYASHI , Shigenori SATO
IPC分类号: H01L27/24 , H01L27/115 , H01L45/00
CPC分类号: H01L45/16 , H01L27/11565 , H01L27/11575 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146
摘要: A wedge-shaped contact region can be employed to provide electrical contacts to multiple electrically conductive layers in a three-dimensional device structure. A cavity including a generally wedge-shaped region and a primary region is formed in a dielectric matrix layer over a support structure. An alternating stack of insulating layers and electrically conductive layers is formed by a series of conformal deposition processes in the cavity and over the dielectric matrix layer. The alternating stack can be planarized employing the top surface of the dielectric matrix layer as a stopping layer. A tip portion of each electrically conductive layer within remaining portions of the alternating stack is laterally offset from the tip of the generally wedge-shaped region by a respective lateral offset distance along a lateral protrusion direction. Contact via structures can be formed on the tip portions of the electrically conductive layers to provide electrical contact.
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公开(公告)号:US09985205B2
公开(公告)日:2018-05-29
申请号:US15061328
申请日:2016-03-04
发明人: Yusuke Arayashiki
IPC分类号: H01L27/24 , H01L45/00 , H01L27/118
CPC分类号: H01L45/145 , G11C2207/105 , H01L27/2481 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/146 , H01L45/148 , H01L45/16 , H01L2027/11885 , H01L2027/11887 , H01L2224/05553 , H01L2224/05554
摘要: According to one embodiment, a semiconductor memory device includes first and second interconnect parts, and a second interconnect connection part. The first interconnect part includes a first core part, and a first interconnect layer. The first interconnect layer includes a first surrounding region and a first extended region. The second interconnect part includes a second core part, and a second interconnect layer. The second interconnect layer includes a second surrounding region and a second extended region. The second extended connection part overlaps a part of the first extended region in the third direction, overlaps the second core part in the first direction, and is electrically connected to the second core part. The second extended surrounding part is provided around the second extended connection part and contains a material contained in the first surrounding region.
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