-
公开(公告)号：US11875865B2
公开(公告)日：2024-01-16
申请号：US17670111
申请日：2022-02-11
发明人： Falgun G. Trivedi
CPC分类号： G11C16/3495 , G11C16/102 , G11C16/26 , G11C16/3404
摘要： A method includes determining a programmed threshold voltage for a select gate of a memory string and assigning the select gate a programmed reliability rank based upon the programmed threshold voltage. The programmed reliability rank indicates that hot data, warm data, and/or or cold data are programmable to the memory string. The method further includes incrementing a quality characteristic count to a first check voltage value, determining a first checked threshold voltage for the select gate at the first check voltage value, and assigning the select gate a first reliability rank based upon the first checked threshold voltage. The first reliability rank indicates that the warm data or the cold data, or both, are programmable to the memory string.
-
公开(公告)号：US11875854B2
公开(公告)日：2024-01-16
申请号：US17710683
申请日：2022-03-31
发明人： Teng Hao Yeh , Wu-Chin Peng , Chih-Ming Lin , Hang-Ting Lue
摘要： A memory device and a word line driver thereof are provided. The word line driver includes a first word line signal generator, a second word line signal generator, a first voltage generator, and a second voltage generator. The first word line signal generator selects one of a first voltage and a second voltage to generate a first word line signal according a control signal. The second word line signal generator selects one of a third voltage and a fourth voltage to generate a second word line signal according the control signal. The first voltage generator provides the second voltage, and the second voltage generator provides the fourth voltage, where the first voltage generator is independent to the second voltage generator.
-
公开(公告)号：US11854611B2
公开(公告)日：2023-12-26
申请号：US17326417
申请日：2021-05-21
发明人： Harish Singidi , Amiya Banerjee , Shantanu Gupta
IPC分类号： G11C11/34 , G11C11/56 , G11C16/04 , G11C16/16 , G11C16/34 , G11C16/10 , H10B41/27 , H10B43/27
CPC分类号： G11C11/5628 , G11C11/5635 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/3445 , G11C16/3459 , H10B41/27 , H10B43/27
摘要： A multiphase programming scheme for programming a plurality of memory cells of a data storage system includes a first programming phase in which a first set of voltage distributions of the plurality of memory cells is programmed by applying a first plurality of program pulses to word lines of the plurality of memory cells, and a second programming phase in which a second set of voltage distributions is programmed by applying a second plurality of program pulses to the word lines of the plurality of memory cells. The second programming phase includes maintaining a margin of separation between two adjacent voltage distributions of the second set of voltage distributions after each of the second plurality of program pulses. This scheme achieves better margin using an aggressive quick pass approach, which helps with data recovery in case of power loss events.
-
公开(公告)号：US11830559B2
公开(公告)日：2023-11-28
申请号：US17348886
申请日：2021-06-16
申请人： Kioxia Corporation
发明人： Noboru Shibata
CPC分类号： G11C16/3445 , G11C16/10 , G11C16/14 , G11C16/26
摘要： In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≤n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
-
公开(公告)号：US11830555B2
公开(公告)日：2023-11-28
申请号：US17358749
申请日：2021-06-25
CPC分类号： G11C16/102 , G11C16/08 , G11C16/26 , G11C16/30 , G11C16/3495
摘要： A storage device is provided that performs constant biasing in priority blocks, such as OTP memory blocks (fuse ROM) and flash memory blocks having a threshold number of P/E cycles. The storage device includes an OTP memory, a flash memory, and a controller. The OTP memory includes a block having a word line and a plurality of cells coupled to the word line. The flash memory includes another block having a word line and a plurality of cells coupled to this word line. The controller is configured to apply a constant bias to the word line of the OTP memory block and, in some cases to the word line of the flash memory block, between execution of host commands. As a result, lower bit error rates due to wider Vt margins may occur while system power may be saved through selective application of constant biasing.
-
公开(公告)号：US11823744B2
公开(公告)日：2023-11-21
申请号：US17487634
申请日：2021-09-28
发明人： Xiang Yang
CPC分类号： G11C16/22 , G11C16/0483 , G11C16/10 , G11C16/26
摘要： A method of operating a memory device. The method includes the step of preparing a memory device that includes a first group of the memory holes with full SGD transistors and a second group of the memory holes with partial SGD transistors. The second group includes both a set of selected partial SGD transistors and a set of unselected partial SGD transistors. The method proceeds with electrically floating a first unselected partial SGD transistor of the set of unselected partial SGD transistors. With the at least one first unselected partial SGD transistor electrically floating, the method continues with reducing a voltage applied to at least one transistor or memory cell adjacent the first unselected partial SGD transistor such that a voltage of the first unselected partial SGD transistor is decreased through a capacitance coupling effect.
-
公开(公告)号：US11804259B2
公开(公告)日：2023-10-31
申请号：US17715370
申请日：2022-04-07
申请人： Rambus Inc.
IPC分类号： G11C11/34 , G11C11/4091 , G06F11/10 , G11C11/4076
CPC分类号： G11C11/4091 , G06F11/10 , G06F11/1004 , G11C11/4076 , G11C2207/2263
摘要： Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.
-
18.发明授权公开(公告)号：US11778806B2
公开(公告)日：2023-10-03
申请号：US17388678
申请日：2021-07-29
发明人： Eric S. Carman , Durai Vishak Nirmal Ramaswamy , Richard E Fackenthal , Kamal M. Karda , Karthik Sarpatwari , Haitao Liu , Duane R. Mills , Christian Caillat
IPC分类号： G11C11/34 , H10B12/00 , H01L29/24 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C11/4094 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40
CPC分类号： H10B12/20 , G11C11/4074 , G11C11/4085 , G11C11/4094 , G11C11/4096 , H01L29/24 , H10B12/50 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40
摘要： Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.
-
公开(公告)号：US11769550B2
公开(公告)日：2023-09-26
申请号：US17736220
申请日：2022-05-04
IPC分类号： G11C11/34 , G11C11/417 , G11C5/14 , G11C11/412
CPC分类号： G11C11/417 , G11C5/147 , G11C5/148 , G11C11/412
摘要： Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.
-
公开(公告)号：US11749352B2
公开(公告)日：2023-09-05
申请号：US17230032
申请日：2021-04-14
申请人： Kioxia Corporation
发明人： Yasushi Nagadomi
IPC分类号： G11C11/34 , G11C16/14 , G11C11/56 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/08 , G11C16/26 , G11C16/34
CPC分类号： G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3459
摘要： A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.
-
-
-
-
-
-
-
-
-
搜索结果
8079 条记录 (耗时 0.03 秒)
