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    Semiconductor device
    193.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US09673224B2

    公开(公告)日：2017-06-06

    申请号：US14515993

    申请日：2014-10-16

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shunpei Yamazaki ,  Shuhei Nagatsuka ,  Tatsuya Onuki ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Hidekazu Miyairi

    IPC: H01L27/12 ,  H01L29/423 ,  H01L29/786

    CPC classification number: H01L27/1225 ,  H01L29/42384 ,  H01L29/7869 ,  H01L29/78696

    Abstract: To provide a semiconductor device that is suitable for miniaturization. The semiconductor device includes a first transistor, a second transistor over the first transistor, a barrier layer between the first transistor and the second transistor, a first electrode between the first transistor and the barrier layer, and a second electrode between the hairier layer and the second transistor and overlapping the first electrode with the barrier layer therebetween. A gate electrode of the first transistor, the first electrode, one of a source electrode and a drain electrode of the second transistor are electrically connected to one another. A channel is formed in a first semiconductor layer including a single crystal semiconductor in the first transistor. A channel is formed in a second semiconductor layer including an oxide semiconductor in the second transistor.

    Semiconductor device
    195.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09443880B2

    公开(公告)日：2016-09-13

    申请号：US14500445

    申请日：2014-09-29

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Toshihiko Saito ,  Yuki Hata ,  Kiyoshi Kato

    IPC: H01L27/12 ,  H01L27/115 ,  H01L49/02 ,  G11C16/04

    CPC classification number: H01L27/124 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1225 ,  H01L28/40

    Abstract: An object is to miniaturize a semiconductor device. Another object is to reduce the area of a driver circuit of a semiconductor device including a memory cell. The semiconductor device includes an element formation layer provided with at least a first semiconductor element, a first wiring provided over the element formation layer, an interlayer film provided over the first wiring, and a second wiring overlapping with the first wiring with the interlayer film provided therebetween. The first wiring, the interlayer film, and the second wiring are included in a second semiconductor element. The first wiring and the second wiring are wirings to which the same potentials are supplied.

    Abstract translation: 目的是使半导体器件小型化。 另一个目的是减小包括存储单元的半导体器件的驱动电路的面积。 半导体器件包括至少设置有第一半导体元件的元件形成层，设置在元件形成层上的第一布线，设置在第一布线上的中间膜，和与第一布线重叠的第二布线，设置有夹层膜 之间。 第一布线，层间膜和第二布线包括在第二半导体元件中。 第一布线和第二布线是提供相同电位的布线。

    Microcontroller capable of being in three modes
    197.
    发明授权
    Microcontroller capable of being in three modes 有权
    能够处于三种模式的微控制器

    公开(公告)号：US09423860B2

    公开(公告)日：2016-08-23

    申请号：US14013082

    申请日：2013-08-29

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tatsuji Nishijima ,  Hidetomo Kobayashi ,  Tomoaki Atsumi ,  Kiyoshi Kato

    IPC: G06F1/00 ,  G06F1/32 ,  G11C11/405 ,  G11C5/14

    CPC classification number: G06F1/3243 ,  G06F1/3287 ,  G11C5/148 ,  G11C11/405 ,  Y02D10/152 ,  Y02D10/171

    Abstract: To provide a microcontroller that can operate in a low power consumption mode. The microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register of the peripheral circuit is formed at an interface with a bus line. A power gate is provided for control of power supply, and the microcontroller can operate in the low power consumption mode where some circuits alone are active, in addition to in a normal operation mode where all circuits are active. A register with no power supply in the low power consumption mode, such as a register of the CPU, includes a volatile memory and a nonvolatile memory.

    Abstract translation: 提供可在低功耗模式下工作的微控制器。 微控制器包括CPU，存储器和诸如定时器电路的外围电路。 外围电路的寄存器形成在与总线线路的接口处。 提供电源门用于控制电源，并且除了在所有电路都处于活动状态的正常操作模式之外，微控制器可以以低功耗模式操作，其中一些电路单独有效。 在低功耗模式下没有电源的寄存器（例如CPU的寄存器）包括易失性存储器和非易失性存储器。

    Memory device
    199.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US09196616B2

    公开(公告)日：2015-11-24

    申请号：US14227408

    申请日：2014-03-27

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi Kato ,  Toshihiko Saito

    IPC: H01L29/10 ,  H01L27/108 ,  H01L29/94 ,  H01L21/84 ,  H01L27/12 ,  H01L49/02

    CPC classification number: H01L27/10808 ,  H01L21/84 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/1203 ,  H01L28/91

    Abstract: It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.

    Abstract translation: 本发明的目的是提供一种存储器单元所占据的区域小的存储器件，而且存储器单元所占据的区域小且数据保持期间长的存储器件。 存储器件包括位线，电容器，设置在位线上并包括沟槽部分的第一绝缘层，半导体层，与半导体层接触的第二绝缘层，以及与第二绝缘层接触的字线 绝缘层。 半导体层的一部分电连接到槽部的底部的位线，半导体层的另一部分与第一绝缘层的上表面的电容器的一个电极电连接。

    Method for driving semiconductor device and semiconductor device
    200.
    发明授权
    Method for driving semiconductor device and semiconductor device 有权
    半导体器件和半导体器件的驱动方法

    公开(公告)号：US09171630B2

    公开(公告)日：2015-10-27

    申请号：US14201068

    申请日：2014-03-07

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shuhei Nagatsuka ,  Hiroki Inoue ,  Takahiko Ishizu ,  Takanori Matsuzaki ,  Yutaka Shionoiri ,  Kiyoshi Kato

    IPC: G11C16/24 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08

    CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C16/0433 ,  G11C16/08

    Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The electrical charge of a bit line is discharged, the potential of the bit line is charged via a transistor for writing data, and the potential of the bit line which is changed by the charging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

    Abstract translation: 从具有使用硅的晶体管的存储单元和使用氧化物半导体的晶体管读取多电平数据，而不用根据多电平数据的电平数来切换用于读取多电平数据的信号。 放电位线的电荷，通过用于写入数据的晶体管对位线的电位进行充电，并且通过充电而改变的位线的电位被读取为多电平数据。 通过这样的结构，可以通过仅读取数据的信号的一次切换来读取对应于保持在晶体管的栅极中的数据的电位。

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