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    Method of forming split-gate memory cell array along with low and high voltage logic devices
    201.
    发明授权
    Method of forming split-gate memory cell array along with low and high voltage logic devices 有权
    与低压和高压逻辑器件一起形成分离栅极存储单元阵列的方法

    公开(公告)号：US09496369B2

    公开(公告)日：2016-11-15

    申请号：US15002307

    申请日：2016-01-20

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Man-Tang Wu ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Chun-Ming Chen ,  Nhan Do

    IPC: H01L21/336 ,  H01L29/66 ,  H01L29/423 ,  H01L27/115

    CPC classification number: H01L29/66537 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825

    Abstract: A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.

    Abstract translation: 一种在具有存储器，LV和HV区域的衬底上形成存储器件的方法，包括在存储区域中形成间隔开的存储堆叠对，在衬底上形成第一导电层并与衬底绝缘，在第一绝缘层上形成第一绝缘层 第一导电层并将其从存储器和HV区域中移除，执行导电材料沉积以增厚存储器和HV区域中的第一导电层，并在LV区域的第一绝缘层上形成第二导电层， 蚀刻以使存储器和HV区域中的第一导电层变薄，并且去除LV区域中的第二导电层，从LV区域移除第一绝缘层，以及图案化第一导电层以形成第一导电层的块 记忆，LV和HV区域。

    Formation of self-aligned source for split-gate non-volatile memory cell
    202.
    发明授权
    Formation of self-aligned source for split-gate non-volatile memory cell 有权
    分离门非易失性存储单元的自对准源的形成

    公开(公告)号：US09484261B2

    公开(公告)日：2016-11-01

    申请号：US14319893

    申请日：2014-06-30

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Yueh-Hsin Chen

    IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/823425 ,  H01L29/1608 ,  H01L29/42328 ,  H01L29/66825

    Abstract: A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.

    Abstract translation: 一种具有一对导电浮动栅极的存储器件，所述导电浮动栅极具有彼此相对的内侧壁，并且设置在第一导电类型的衬底上并与其绝缘。 一对间隔开的导电控制栅极，每个导电控制栅极设置在浮动栅极中的一个上并与其绝缘，并且每个包括面向彼此的内侧壁。 一对绝缘材料的第一间隔物，沿着控制栅极内侧壁和浮动栅极延伸。 浮动门内侧壁与第一间隔件的侧表面对准。 绝缘材料的一对第二间隔物各自沿着第一间隔件中的一个并且沿着浮动栅极内侧壁中的一个延伸。 形成在衬底中的沟槽，其具有与第二间隔物的侧表面对齐的侧壁。 设置在沟槽中的硅碳。 材料注入到硅碳中，形成具有第二导电类型的第一区域。

    Split Gate Non-volatile Memory Cell With 3D FINFET Structure, And Method Of Making Same
    203.
    发明申请
    Split Gate Non-volatile Memory Cell With 3D FINFET Structure, And Method Of Making Same 有权
    具有3D FINFET结构的分离门非易失性存储单元及其制作方法

    公开(公告)号：US20160276357A1

    公开(公告)日：2016-09-22

    申请号：US15050309

    申请日：2016-02-22

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

    IPC: H01L27/115 ,  H01L29/78 ,  H01L29/66 ,  H01L27/105

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11551 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/7881

    Abstract: A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

    Abstract translation: 一种非易失性存储单元，包括具有上表面和两个侧表面的鳍形上表面的半导体衬底。 源极和漏极区域形成在鳍状上表面部分中，其间具有沟道区域。 导电浮栅包括沿着顶表面的第一部分延伸的第一部分，以及分别沿两个侧表面的第一部分延伸的第二和第三部分。 导电控制栅极包括沿着顶表面的第二部分延伸的第一部分，分别沿两个侧表面的第二部分延伸的第二部分和第三部分，第一部分和第二部分， 以及分别延伸至少一些所述浮动栅极第二和第三部分的第五和第六部分。

    Integration Of Split Gate Flash Memory Array And Logic Devices
    205.
    发明申请
    Integration Of Split Gate Flash Memory Array And Logic Devices 有权
    分流门闪存阵列和逻辑器件的集成

    公开(公告)号：US20160260728A1

    公开(公告)日：2016-09-08

    申请号：US15057590

    申请日：2016-03-01

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chun-Ming Chen ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Man-Tang Wu ,  Nhan Do

    IPC: H01L27/115 ,  H01L29/423

    CPC classification number: H01L27/11531 ,  G11C16/0425 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/66825

    Abstract: A memory device and method including a semiconductor substrate with memory and logic device areas. A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.

    Abstract translation: 一种存储器件和方法，包括具有存储器和逻辑器件区域的半导体衬底。 多个存储单元形成在存储区域中，每个存储单元包括第一源极和漏极区域，其间具有第一沟道区域，布置在第一沟道区域的第一部分上方的浮置栅极，设置在浮置栅极上的控制栅极， 设置在第一通道区域的第二部分上的选择栅极和设置在源极区域上的擦除栅极。 形成在逻辑器件区域中的多个逻辑器件，每个逻辑器件包括在其间具有第二沟道区域的第二源极和漏极区域以及设置在第二沟道区域上的逻辑门极。 衬底上表面在存储器区域中比在逻辑器件区域中凹陷更低，使得较高的存储器单元具有与逻辑器件类似的上部高度。

    Method Of Forming Split-Gate Memory Cell Array Along With Low And High Voltage Logic Devices
    207.
    发明申请
    Method Of Forming Split-Gate Memory Cell Array Along With Low And High Voltage Logic Devices 有权
    与低和高电压逻辑器件一起形成分离栅极存储器单元阵列的方法

    公开(公告)号：US20160218195A1

    公开(公告)日：2016-07-28

    申请号：US15002307

    申请日：2016-01-20

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Man-Tang Wu ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Chun-Ming Chen ,  Nhan Do

    IPC: H01L29/66 ,  H01L27/115

    CPC classification number: H01L29/66537 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825

    Abstract: A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.

    Abstract translation: 一种在具有存储器，LV和HV区域的衬底上形成存储器件的方法，包括在存储区域中形成间隔开的存储堆叠对，在衬底上形成第一导电层并与衬底绝缘，在第一绝缘层上形成第一绝缘层 第一导电层并将其从存储器和HV区域中移除，执行导电材料沉积以增厚存储器和HV区域中的第一导电层，并在LV区域的第一绝缘层上形成第二导电层， 蚀刻以使存储器和HV区域中的第一导电层变薄，并且去除LV区域中的第二导电层，从LV区域移除第一绝缘层，以及图案化第一导电层以形成第一导电层的块 记忆，LV和HV区域。

    Method of making split-gate memory cell with substrate stressor region
    209.
    发明授权
    Method of making split-gate memory cell with substrate stressor region 有权
    具有衬底应力区域的分裂栅极存储器单元的方法

    公开(公告)号：US09306039B2

    公开(公告)日：2016-04-05

    申请号：US14665079

    申请日：2015-03-23

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Mandana Tadayoni ,  Nhan Do

    IPC: H01L21/336 ,  H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L29/778 ,  H01L21/28 ,  H01L27/115 ,  H01L29/78

    CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/1054 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/788

    Abstract: A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.

    Abstract translation: 一种存储器件及其制造方法，具有第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，衬底中的沟道区域，导电浮动 栅极覆盖并与衬底绝缘，其中浮置栅极至少部分地布置在第一区域和通道区域的第一部分之上，导电第二栅极横向邻近并与浮动栅极绝缘，其中第二栅极被布置 至少部分地覆盖并与沟道区的第二部分绝缘，以及形成在第二栅极下方的衬底中的嵌入碳化硅的应力区域。

    Non-volatile memory array with concurrently formed low and high voltage logic devices
    210.
    发明授权
    Non-volatile memory array with concurrently formed low and high voltage logic devices 有权
    具有同时形成的低和高电压逻辑器件的非易失性存储器阵列

    公开(公告)号：US09276005B1

    公开(公告)日：2016-03-01

    申请号：US14560475

    申请日：2014-12-04

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Feng Zhou ,  Xian Liu ,  Nhan Do

    IPC: H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66

    CPC classification number: H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

    Abstract: A memory cell includes source and drain regions in a substrate with a channel region therebetween, an erase gate over the source region, a floating gate over a first channel region portion, a control gate over the floating gate, and a wordline gate over a second channel region portion. A first logic device includes second source and drain regions in the substrate with a second channel region therebetween under a first logic gate. A second logic device includes third source and drain regions in the substrate with a third channel region therebetween under a second logic gate. The wordline gate and the first and second logic gates comprise the same conductive metal material. The second logic gate is insulated from the third channel region by first and second insulation. The first logic gate is insulated from the second channel region by the second insulation and not by the first insulation.

    Abstract translation: 存储单元包括在其中具有沟道区域的衬底中的源极和漏极区域，源极区域上的擦除栅极，在第一沟道区域部分上的浮动栅极，浮置栅极上的控制栅极以及第二沟道区域上的字线栅极 通道区域部分。 第一逻辑器件包括衬底中的第二源极和漏极区域，在第一逻辑门之下具有第二沟道区域。 第二逻辑器件包括衬底中的第三源极和漏极区域，在第二逻辑门极之间具有第三沟道区域。 字线栅极和第一和第二逻辑门包括相同的导电金属材料。 第二逻辑门通过第一和第二绝缘与第三沟道区绝缘。 第一逻辑门通过第二绝缘而与第二沟道区绝缘，而不是通过第一绝缘。

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