公开(公告)号：US20190198673A1

公开(公告)日：2019-06-27

申请号：US15890530

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Albert Fayrushin

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L29/78391 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/512 ,  H01L29/513 ,  H01L29/516

Abstract: A programmable charge-storage transistor comprises channel material, insulative charge-passage material, charge-storage material, a control gate, and charge-blocking material between the charge-storage material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material. Arrays of elevationally-extending strings of memory cells of memory cells are disclosed, including methods of forming such. Other embodiments, including method, are disclosed.

公开(公告)号：US20190189515A1

公开(公告)日：2019-06-20

申请号：US15843493

申请日：2017-12-15

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  John A. Smythe ,  Haitao Liu ,  Richard J. Hill ,  Deepak Chandra Pandey

IPC: H01L21/8239 ,  H01L21/8229 ,  H01L21/8234 ,  H01L29/10 ,  G11C11/40

CPC classification number: H01L21/8239 ,  G11C11/40 ,  G11C2211/4016 ,  H01L21/8229 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/105

Abstract: An embodiment of the invention comprises a method of forming a transistor comprising forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction. Tops of the semiconductor material and the conductive gate material are covered with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material are laterally exposed above both of the sides of the gate construction. After the covering, the semiconductor material that is above both of the sides of the gate construction is subjected to monolayer doping through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.

公开(公告)号：US20190181143A1

公开(公告)日：2019-06-13

申请号：US16279262

申请日：2019-02-19

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Chandra Mouli ,  Sanh D. Tang

IPC: H01L27/108 ,  H01L29/78

Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.

公开(公告)号：US10217753B2

公开(公告)日：2019-02-26

申请号：US15861286

申请日：2018-01-03

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Qian Tao ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Kirk D. Prall ,  Ashonita Chavan

IPC: H01L27/00 ,  H01G4/08 ,  H01L27/11502 ,  H01L27/11507 ,  H01L49/02 ,  H01L27/108

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

公开(公告)号：US20190051653A1

公开(公告)日：2019-02-14

申请号：US16161381

申请日：2018-10-16

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kamal M. Karda ,  Wolfgang Mueller ,  Sourabh Dhir ,  Robert Kerr ,  Sangmin Hwang ,  Haitao Liu

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L23/528

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

公开(公告)号：US20180374855A1

公开(公告)日：2018-12-27

申请号：US15895928

申请日：2018-02-13

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Chandra Mouli ,  Sanh D. Tang

IPC: H01L27/108 ,  H01L29/78

Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.

公开(公告)号：US10026480B2

公开(公告)日：2018-07-17

申请号：US15669311

申请日：2017-08-04

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/16 ,  G11C16/08 ,  G11C11/56 ,  H01L27/105 ,  G11C16/34

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US09887204B2

公开(公告)日：2018-02-06

申请号：US15584371

申请日：2017-05-02

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Qian Tao ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Kirk D. Prall ,  Ashonita A. Chavan

IPC: H01L27/00 ,  H01L27/11502 ,  H01L49/02 ,  H01G4/08 ,  H01L27/11507 ,  H01L27/108

CPC classification number: H01L27/11502 ,  H01G4/08 ,  H01L27/10805 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/40 ,  H01L28/75

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

公开(公告)号：US09881686B2

公开(公告)日：2018-01-30

申请号：US15393719

申请日：2016-12-29

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

公开(公告)号：US09773888B2

公开(公告)日：2017-09-26

申请号：US14190807

申请日：2014-02-26

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Haitao Liu ,  Sanh D. Tang ,  Wolfgang Mueller ,  Sourabh Dhir

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/7827

Abstract: A vertical access device comprises a semiconductive base comprising a first source/drain region, a semiconductive pillar extending vertically from the semiconductive base, and a gate electrode adjacent a sidewall of the semiconductive pillar. The semiconductive pillar comprises a channel region overlying the first source/drain region, and a second source/drain region overlying the channel region. An opposing sidewall of the semiconductive pillar is not adjacent the gate electrode or another gate electrode. Semiconductive device structures, methods of forming a vertical access device, and methods of forming a semiconductive structure are also described.