CLOCK PHASE SHIFT CIRCUIT
    211.
    发明申请
    CLOCK PHASE SHIFT CIRCUIT 有权
    时钟相移电路

    公开(公告)号:US20160373093A1

    公开(公告)日:2016-12-22

    申请号:US14754778

    申请日:2015-06-30

    Inventor: Yong Feng Liu

    CPC classification number: H03K5/00 H03K5/135 H03K2005/00202

    Abstract: An electronic device includes a first circuit to generate an output control signal when a first voltage across a first capacitor receiving an input current exceeds a threshold voltage, in response to an input signal having a first logic level. The input current is proportional to a frequency of the input signal. A second circuit is to generate an output reset signal when a second voltage across a second capacitor receiving the input current exceeds the threshold voltage, in response to the input signal having a second logic level. A flip flop is to generate a signal output as having the first logic level in response to the output control signal, and to reset and generate the signal output as having the second logic level in response to the output reset signal.

    Abstract translation: 电子设备包括第一电路,用于响应于具有第一逻辑电平的输入信号,当接收输入电流的第一电容器两端的第一电压超过阈值电压时产生输出控制信号。 输入电流与输入信号的频率成比例。 第二电路是响应于输入信号具有第二逻辑电平而在接收输入电流的第二电容器两端的第二电压超过阈值电压时产生输出复位信号。 触发器是响应于输出控制信号而产生具有第一逻辑电平的信号输出,并且响应于输出复位信号复位并产生具有第二逻辑电平的信号输出。

    LDO REGULATOR WITH IMPROVED LOAD TRANSIENT PERFORMANCE FOR INTERNAL POWER SUPPLY

    公开(公告)号:US20160357206A1

    公开(公告)日:2016-12-08

    申请号:US15244289

    申请日:2016-08-23

    Inventor: Yong Feng Liu

    CPC classification number: G05F1/575 G05F1/565 G05F1/59 G05F3/30

    Abstract: A voltage regulator includes a feedback regulation loop and a drive transistor configured to source current to a regulated output. A transient recovery circuit is coupled to the voltage regulator circuit and includes a first transistor coupled to source current into a control terminal of the drive transistor, wherein the source current is in addition to current sourced in response to operation of the feedback regulation loop. The first transistor is selectively actuated in response to a drop in voltage at the regulated output. The transient recovery circuit further includes a second transistor coupled to sink current from the regulated output. The sink current has a first non-zero magnitude in the quiescent operating mode of the regulator circuit. In response to an increase in voltage at the regulated output, the operation of the second transistor is modified to increase the sink current to a second, greater, non-zero magnitude.

    HIGH EFFICIENCY CLASS D AMPLIFIER WITH REDUCED GENERATION OF EMI
    213.
    发明申请
    HIGH EFFICIENCY CLASS D AMPLIFIER WITH REDUCED GENERATION OF EMI 有权
    具有降低EMI产生的高效级D放大器

    公开(公告)号:US20160329868A1

    公开(公告)日:2016-11-10

    申请号:US14715879

    申请日:2015-05-19

    Abstract: A class-D amplifier includes a signal processing block. The signal processing block generates a first processed signal representing a difference between a first differential signal and a second differential signal, when a duty cycle of the first differential signal is greater than that of the second differential signal. The signal processing block generates the first processed signal representing a reference DC level, when the duty cycle of the first differential signal is less than that of the second differential signal. A second processed signal representing a difference between the second differential signal and the first differential signal is generated when the duty cycle of the second differential signal is greater than that of the first differential signal, and the second processed signal representing the reference DC level is generated when the duty cycle of the second differential signal is less than that of the first differential signal.

    Abstract translation: D类放大器包括信号处理块。 当第一差分信号的占空比大于第二差分信号的占空比时,信号处理块产生表示第一差分信号和第二差分信号之间的差的第一处理信号。 当第一差分信号的占空比小于第二差分信号的占空比时,信号处理块产生表示参考DC电平的第一处理信号。 当第二差分信号的占空比大于第一差分信号的占空比时,产生表示第二差分信号和第一差分信号之间的差的第二处理信号,并且生成表示参考DC电平的第二处理信号 当第二差分信号的占空比小于第一差分信号的占空比时。

    LDO regulator with improved load transient performance for internal power supply
    217.
    发明授权
    LDO regulator with improved load transient performance for internal power supply 有权
    LDO稳压器,内部电源具有改善的负载瞬态性能

    公开(公告)号:US09454166B2

    公开(公告)日:2016-09-27

    申请号:US14543294

    申请日:2014-11-17

    Inventor: Yong Feng Liu

    CPC classification number: G05F1/575 G05F1/565 G05F1/59 G05F3/30

    Abstract: A voltage regulator includes a feedback regulation loop and a drive transistor configured to source current to a regulated output. A transient recovery circuit is coupled to the voltage regulator circuit and includes a first transistor coupled to source current into a control terminal of the drive transistor, wherein the source current is in addition to current sourced in response to operation of the feedback regulation loop. The first transistor is selectively actuated in response to a drop in voltage at the regulated output. The transient recovery circuit further includes a second transistor coupled to sink current from the regulated output. The sink current has a first non-zero magnitude in the quiescent operating mode of the regulator circuit. In response to an increase in voltage at the regulated output, the operation of the second transistor is modified to increase the sink current to a second, greater, non-zero magnitude.

    Abstract translation: 电压调节器包括反馈调节环路和驱动晶体管,其被配置为将电流输出到调节输出端。 瞬态恢复电路耦合到电压调节器电路,并且包括耦合到源极电流到驱动晶体管的控制端的第一晶体管,其中源电流除了响应于反馈调节环的操作而产生的电流之外。 第一晶体管响应于调节输出处的电压下降而选择性地致动。 瞬态恢复电路还包括耦合到从调节输出吸收电流的第二晶体管。 灌电流在调节器电路的静态工作模式下具有第一个非零幅值。 响应于调节输出处的电压增加,第二晶体管的操作被修改以将吸收电流增加到第二,更大,非零的幅度。

    Voltage slope control method and apparatus for power driver circuit application
    218.
    发明授权
    Voltage slope control method and apparatus for power driver circuit application 有权
    电力斜坡控制方法和电源驱动电路应用的装置

    公开(公告)号:US09236854B2

    公开(公告)日:2016-01-12

    申请号:US13888843

    申请日:2013-05-07

    CPC classification number: H03K5/12

    Abstract: A drive circuit includes a first transistor coupled in series with a second transistor at a first intermediate node coupled to a load. An amplifier has an output driving a control terminal of the second transistor. The amplifier includes a first input coupled to a second intermediate node and a second input coupled to a reference voltage. A feedback circuit is coupled between the first intermediate node and the second intermediate node. A slope control circuit is coupled the second intermediate node. The slope control circuit injects a selected value of current into the second intermediate node, that current operating to control the output of the amplifier in setting a slope for change in voltage at the first intermediate node.

    Abstract translation: 驱动电路包括与耦合到负载的第一中间节点与第二晶体管串联耦合的第一晶体管。 放大器具有驱动第二晶体管的控制端的输出。 放大器包括耦合到第二中间节点的第一输入和耦合到参考电压的第二输入。 反馈电路耦合在第一中间节点和第二中间节点之间。 斜坡控制电路耦合第二中间节点。 斜坡控制电路将选择的电流值注入到第二中间节点中,该电流在设定第一中间节点处电压变化的斜率时控制放大器的输出。

    DRIVER CIRCUIT WITH GATE CLAMP SUPPORTING STRESS TESTING
    219.
    发明申请
    DRIVER CIRCUIT WITH GATE CLAMP SUPPORTING STRESS TESTING 有权
    带门夹的驱动电路支持应力测试

    公开(公告)号:US20150381148A1

    公开(公告)日:2015-12-31

    申请号:US14449232

    申请日:2014-08-01

    Inventor: Ni Zeng

    Abstract: A generator circuit is coupled to apply a control signal the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.

    Abstract translation: 发电机电路被耦合以施加驱动输出节点的功率晶体管的栅极端子的控制信号。 产生参考电压,其具有第一电压值作为控制信号的基准,并具有用于应力测试的第二,较高的电压值。 在参考电压和功率晶体管栅极之间提供钳位电路,以在两种模式下起作用。 在一种模式中,当发电机电路施加控制信号时,钳位电路施加第一钳位电压以钳位功率晶体管的栅极处的电压。 在另一种模式下,钳位电路在栅极压力测试期间施加第二个较高的钳位电压来钳位功率晶体管的栅极。

    CURRENT SLOPE CONTROL METHOD AND APPARTUS FOR POWER DRIVER CIRCUIT APPLICATION
    220.
    发明申请
    CURRENT SLOPE CONTROL METHOD AND APPARTUS FOR POWER DRIVER CIRCUIT APPLICATION 有权
    电流控制方法和电源驱动电路应用

    公开(公告)号:US20150339963A1

    公开(公告)日:2015-11-26

    申请号:US14818924

    申请日:2015-08-05

    Abstract: A low side driver includes a first transistor coupled in series with a second transistor at a low side voltage node for a load. A capacitance is configured to store a voltage and a voltage buffer circuit has an input coupled to receive the voltage stored by the capacitance and an output coupled to drive a control node of the second transistor with the stored voltage. A current source supplies current through a switch to the capacitance and the input of the voltage buffer circuit. The switch is configured to be actuated by an oscillating enable signal so as to cyclically source current from the current source to the capacitance and cause a stepped increase in the stored voltage which is applied by the buffer circuit to the control node of the second transistor.

    Abstract translation: 低侧驱动器包括与用于负载的低侧电压节点与第二晶体管串联耦合的第一晶体管。 电容被配置为存储电压,并且电压缓冲器电路具有耦合以接收由电容存储的电压的输入和耦合以用所存储的电压驱动第二晶体管的控制节点的输出。 电流源通过开关将电流提供给电容和电压缓冲电路的输入。 该开关被配置为由振荡使能信号激励,以便将来自电流源的电流循环地引导到电容,并且使由缓冲电路施加到第二晶体管的控制节点的存储电压发生阶梯式增加。

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