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    Non-volatile Memory Program Algorithm Device And Method
    222.
    发明申请
    Non-volatile Memory Program Algorithm Device And Method 有权
    非易失性存储器程序算法设备与方法

    公开(公告)号：US20140269058A1

    公开(公告)日：2014-09-18

    申请号：US14214097

    申请日：2014-03-14

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Xian Liu ,  James Cheng ,  Dmitry Bavinov ,  Alexander Kotov ,  Jong-Won Yoo

    IPC: G11C16/34 ,  G11C16/12

    CPC classification number: G11C16/3486 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459

    Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.

    Abstract translation: 一种用于使用编程电压的重复脉冲编程单元的非易失性存储器件和方法，具有交错读取操作以确定读取电流的电平，直到达到期望的编程状态。 每个连续的编程脉冲具有相对于先前脉冲增加阶跃值的一个或多个编程电压。 对于单级单元类型，在达到第一读取电流阈值之后，每个单元从编程脉冲中单独地移除，并且此后的一个或多个猝发脉冲的步长值增加。 对于多级单元类型，步长值在其中一个单元达到第一读取电流阈值后下降，一些单元在达到第二读取电流阈值之后单独地从编程脉冲中移除，而其他单元在编程脉冲之后被单独从编程脉冲中移除 达到第三个读取电流阈值。

    Non-volatile Memory Cells With Enhanced Channel Region Effective Width, And Method Of Making Same
    223.
    发明申请
    Non-volatile Memory Cells With Enhanced Channel Region Effective Width, And Method Of Making Same 有权
    具有增强通道区域有效宽度的非易失性存储单元及其制作方法

    公开(公告)号：US20140264539A1

    公开(公告)日：2014-09-18

    申请号：US14191625

    申请日：2014-02-27

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Hieu Van Tran ,  Chien-Sheng Su ,  Prateep Tuntasood

    IPC: H01L27/115

    CPC classification number: H01L21/76224 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

    Abstract: A memory device array with spaced apart parallel isolation regions formed in a semiconductor substrate, with an active region between each pair of adjacent isolation regions. Each isolation region includes a trench formed into the substrate surface and an insulation material formed in the trench. Portions of a top surface of the insulation material are recessed below the surface of the substrate. Each active region includes a column of memory cells each having spaced apart first and second regions with a channel region therebetween, a floating gate over a first channel region portion, and a select gate over a second channel region portion. The select gates are formed as continuous word lines extending perpendicular to the isolation regions and each forming the select gates for one row of the memory cells. Portions of each word line extend down into the trenches and disposed laterally adjacent to sidewalls of the trenches.

    Abstract translation: 一种存储器件阵列，其具有形成在半导体衬底中的间隔开的平行隔离区域，在每对相邻隔离区域之间具有有源区域。 每个隔离区域包括形成在衬底表面中的沟槽和形成在沟槽中的绝缘材料。 绝缘材料的顶表面的部分凹陷在基底的表面下方。 每个有源区域包括一列存储单元，每个存储单元具有间隔开的第一和第二区域，其间具有通道区域，在第一沟道区域部分上的浮动栅极以及在第二沟道区域部分上的选择栅极。 选择栅极形成为垂直于隔离区域延伸的连续字线，并且每个形成用于一行存储器单元的选择栅极。 每个字线的一部分向下延伸到沟槽中并且横向设置成与沟槽的侧壁相邻。

    Method of planarizing a semiconductor die
    224.
    发明申请
    Method of planarizing a semiconductor die 有权
    平面化半导体管芯的方法

    公开(公告)号：US20040152397A1

    公开(公告)日：2004-08-05

    申请号：US10762807

    申请日：2004-01-21

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Amitay Levi ,  Gian Sharma

    IPC: B24B001/00

    CPC classification number: H01L21/31055 ,  H01L21/31053

    Abstract: A method of CMP planarizing a silicon dioxide layer on a silicon nitride in the semiconductor die is disclosed. A wafer has a plurality substantially identical semiconductor dies defined on the wafer. Each of the dies is separated from one another by a scribe line. A layer of silicon nitride is formed on the planar surface of the wafer where the silicon nitride has a top surface which is substantially parallel to the planar surface. A layer of silicon dioxide is deposited on the top surface with the silicon dioxide varying in height above the top surface. A mask is formed across the wafer, including on the scribe line, where the mask has a plurality of locations with each location having a differing density of gap-to-pillar ratio, which is proportional to the height of the silicon dioxide above the top surface. The silicon dioxide is anisotropically etched through each gap of the mask across the entire wafer where each gap is etched by the same amount in the height direction. CMP is then used to planarize the silicon dioxide to the top surface of the silicon nitride across the entire wafer.

    Abstract translation: 公开了一种在半导体管芯中的氮化硅上平坦化二氧化硅层的CMP方法。 晶片具有限定在晶片上的多个基本上相同的半导体管芯。 每个模具通过划线彼此分开。 在晶片的平坦表面上形成氮化硅层，其中氮化硅具有基本平行于平面的顶表面。 一层二氧化硅沉积在顶表面上，二氧化硅的高度高于顶表面。 在晶片上形成掩模，包括在划线上，其中掩模具有多个位置，每个位置具有不同的间隙与柱之比的密度，其与顶部上方的二氧化硅的高度成比例 表面。 通过掩模的每个间隙在整个晶片上各向异性蚀刻二氧化硅，其中每个间隙在高度方向上被蚀刻相同的量。 然后使用CMP将二氧化硅平坦化到跨越整个晶片的氮化硅的顶表面。

    Read and programming decoding system for analog neural memory
    226.
    发明授权
    Read and programming decoding system for analog neural memory 有权

    公开(公告)号：US12237011B2

    公开(公告)日：2025-02-25

    申请号：US17853315

    申请日：2022-06-29

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Han Tran ,  Kha Nguyen ,  Hien Pham

    IPC: G11C11/56 ,  G06F17/16 ,  G06N3/06 ,  G11C11/16 ,  G11C11/4074

    Abstract: Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.

    Output circuit
    228.
    发明授权
    Output circuit 有权

    公开(公告)号：US12198043B2

    公开(公告)日：2025-01-14

    申请号：US18522153

    申请日：2023-11-28

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

    IPC: G06N3/065 ,  G06F3/06 ,  G06F17/16 ,  G06N3/08 ,  G11C27/02

    Abstract: In one example, a circuit comprises an input transistor comprising a first terminal, a second terminal coupled to ground, and a gate; a capacitor comprising a first terminal and a second terminal; an output transistor comprising a first terminal providing an output current, a second terminal coupled to ground, and a gate; a first switch; and a second switch; wherein in a first mode, the first switch is closed and couples an input current to the first terminal of the input transistor and the gate of the input transistor and the second switch is closed and couples the first terminal of the input transistor to the first terminal of the capacitor and the gate of the output transistor, and in a second mode, the first switch is open and the second switch is open and the capacitor discharges into the gate of the output transistor.

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