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    Carbon nanotube transistor having extended contacts
    224.
    发明授权
    Carbon nanotube transistor having extended contacts 有权
    碳纳米管晶体管具有延长的触点

    公开(公告)号：US09203041B2

    公开(公告)日：2015-12-01

    申请号：US14169340

    申请日：2014-01-31

    Applicant: International Business Machines Corporation

    Inventor： Shu-Jen Han ,  Wilfried E. Haensch ,  James B. Hannon

    IPC: H01L21/00 ,  H01L51/00 ,  H01L51/05 ,  B82Y10/00

    CPC classification number: H01L51/0545 ,  B82Y10/00 ,  H01L51/0002 ,  H01L51/0048 ,  H01L51/0558

    Abstract: A semiconductor device includes a substrate that extends along a first direction to define a length and second direction perpendicular to the first direction to define a height. The substrate includes a dielectric layer and at least one gate stack formed on the dielectric layer. A source contact is formed adjacent to a first side of the gate stack and a drain contact formed adjacent to an opposing second side of the gate stack. A carbon nanotube is formed on the source contact and the drain contact. A first portion of the nanotube forms a source. A second portion forms a drain. A third portion is interposed between the source and drain to define a gate channel that extends along the first direction. The source and the drain extend along the second direction and have a greater length than the gate channel.

    Abstract translation: 半导体器件包括沿着第一方向延伸以限定垂直于第一方向的长度和第二方向以限定高度的衬底。 衬底包括介电层和形成在电介质层上的至少一个栅叠层。 源极触点形成为邻近栅极堆叠的第一侧，并且与栅极堆叠的相对的第二侧相邻地形成漏极接触。 在源极触点和漏极触点上形成碳纳米管。 纳米管的第一部分形成源。 第二部分形成排水管。 第三部分介于源极和漏极之间以限定沿着第一方向延伸的栅极沟道。 源极和漏极沿着第二方向延伸并且具有比栅极通道更大的长度。

    Self-Aligned III-V MOSFET Fabrication With In-Situ III-V Epitaxy And In-Situ Metal Epitaxy and Contact Formation
    226.
    发明申请
    Self-Aligned III-V MOSFET Fabrication With In-Situ III-V Epitaxy And In-Situ Metal Epitaxy and Contact Formation 审中-公开
    具有原位III-V外延和原位金属外延和接触形成的自对准III-V MOSFET制造

    公开(公告)号：US20150235903A1

    公开(公告)日：2015-08-20

    申请号：US14697991

    申请日：2015-04-28

    Applicant: International Business Machines Corporation

    Inventor： Dechao Guo ,  Shu-Jen Han ,  Jeehwan Kim ,  Kuen-Ting Shiu

    IPC: H01L21/8252 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L29/201 ,  H01L29/08 ,  H01L29/417 ,  H01L21/285 ,  H01L29/207

    CPC classification number: H01L21/8252 ,  H01L21/26546 ,  H01L21/28575 ,  H01L21/3245 ,  H01L29/0847 ,  H01L29/201 ,  H01L29/207 ,  H01L29/41783 ,  H01L29/452 ,  H01L29/66446 ,  H01L29/66477 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/78

    Abstract: A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed.

    Abstract translation: 一种用于形成晶体管的方法，包括提供设置在III-V衬底上的图案化栅极堆叠并且具有形成在图案化栅极叠层的侧面上的侧壁间隔物，III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物 与源/漏区相邻形成的区域。 该方法包括在源极/漏极区域上生长凸起的源极/漏极区域，生长的升高的源极/漏极区域包括III-V半导体材料，以及在生长的升高的源极/漏极区域上生长的金属接触。 形成晶体管的另一种方法包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物 与源/漏区相邻形成的区域。 该方法包括在源/漏区上生长金属接触。 还公开了晶体管和计算机程序产品。

    GRAPHENE DEVICES WITH LOCAL DUAL GATES
    228.
    发明申请
    GRAPHENE DEVICES WITH LOCAL DUAL GATES 有权
    具有本地双门的石墨设备

    公开(公告)号：US20150194536A1

    公开(公告)日：2015-07-09

    申请号：US14661267

    申请日：2015-03-18

    Applicant: International Business Machines Corporation

    Inventor： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

    IPC: H01L29/786 ,  H01L29/16

    CPC classification number: H01L29/66045 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02527 ,  H01L21/044 ,  H01L29/1606 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66015 ,  H01L29/66742 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78684

    Abstract: An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

    Abstract translation: 电子设备包括绝缘体，嵌入在绝缘体中的局部第一栅极，第一栅极的顶表面与绝缘体的表面基本共面;形成在第一栅极和绝缘体上的第一介电层，以及沟道。 通道包括形成在第一介电层上的双层石墨烯层。 第一电介质层提供基本上平坦的表面，在其上形成沟道。 形成在双层石墨烯层上的第二介电层和在第二介电层上形成的局部第二栅极。 局部第一和第二栅极中的每一个电容耦合到双层石墨烯层的沟道。 局部第一和第二栅极形成第一对栅极以局部控制双层石墨烯层的第一部分。

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