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    FIN TRIM PLUG STRUCTURES FOR IMPARTING CHANNEL STRESS
    242.
    发明申请
    FIN TRIM PLUG STRUCTURES FOR IMPARTING CHANNEL STRESS 审中-公开

    公开(公告)号：US20200220016A1

    公开(公告)日：2020-07-09

    申请号：US16240166

    申请日：2019-01-04

    Applicant: Intel Corporation

    Inventor： Leonard GULER ,  Nick LINDERT ,  Biswajeet GUHA ,  Swaminathan SIVAKUMAR ,  Tahir GHANI

    IPC: H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L27/088

    Abstract: Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.

    SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICES ABOVE INSULATOR SUBSTRATES
    243.
    发明申请
    SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICES ABOVE INSULATOR SUBSTRATES 审中-公开

    公开(公告)号：US20200219990A1

    公开(公告)日：2020-07-09

    申请号：US16239090

    申请日：2019-01-03

    Applicant: Intel Corporation

    Inventor： Biswajeet GUHA ,  Dax M. CRUM ,  Stephen M. CEA ,  Leonard P. GULER ,  Tahir GHANI

    IPC: H01L29/66 ,  H01L27/12 ,  H01L21/84

    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.

    GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ASYMMETRIC SOURCE AND DRAIN CONTACT STRUCTURES
    244.
    发明申请
    GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ASYMMETRIC SOURCE AND DRAIN CONTACT STRUCTURES 审中-公开

    公开(公告)号：US20200091348A1

    公开(公告)日：2020-03-19

    申请号：US16134817

    申请日：2018-09-18

    Applicant: Intel Corporation

    Inventor： Biswajeet GUHA ,  Mauro J. KOBRINSKY ,  Tahir GHANI

    IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088

    Abstract: Gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. A first conductive contact structure is coupled to the first epitaxial source or drain structure. A second conductive contact structure is coupled to the second epitaxial source or drain structure. The second conductive contact structure is deeper along the fin than the first conductive contact structure.

    NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME
    247.
    发明申请
    NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME 审中-公开

    公开(公告)号：US20190341383A1

    公开(公告)日：2019-11-07

    申请号：US16510688

    申请日：2019-07-12

    Applicant: Intel Corporation

    Inventor： Tahir GHANI ,  Salman LATIF ,  Chanaka D. MUNASINGHE

    IPC: H01L27/092 ,  H01L29/08 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

    Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

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