公开(公告)号：US5654675A

公开(公告)日：1997-08-05

申请号：US611831

申请日：1996-03-06

Applicant: Melchiorre Bruccoleri ,  Gianfranco Vai ,  Salvatore Portaluri ,  Marco Demicheli

Inventor： Melchiorre Bruccoleri ,  Gianfranco Vai ,  Salvatore Portaluri ,  Marco Demicheli

IPC: H03L7/093 ,  H03L7/089 ,  H03L7/099 ,  H03L7/107

CPC classification number: H03L7/0891 ,  H03L7/099 ,  H03L7/107 ,  H03L2207/04 ,  H03L7/0995

Abstract: A fully integrated, phase locked loop (PLL) having improved jitter characteristics uses the same digital/analog converter (DAC) that is normally used to control the time constant of the low pass loop filter to control the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground. The capacitance introduces a third pole in the loop's transfer function. In this way, the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant; thus, the damping factor remains constant while the .omega..sub.0 of the PLL is varied.

Abstract translation: 具有改进的抖动特性的完全集成的锁相环（PLL）使用相同的数/模转换器（DAC），其通常用于控制低通环路滤波器的时间常数，以控制连接在输出端 压控振荡器和地的电压 - 电流转换输入级。 电容在循环传递函数中引入了第三极点。 以这种方式，传递函数的零和第三极之间的频域分离保持不变; 因此，阻尼因子保持恒定，同时PLL的ω0变化。

公开(公告)号：US5633986A

公开(公告)日：1997-05-27

申请号：US563788

申请日：1995-11-27

Applicant: Gianguido Rizzotto ,  Rinaldo Poluzzi ,  Andrea Pagni

Inventor： Gianguido Rizzotto ,  Rinaldo Poluzzi ,  Andrea Pagni

IPC: G05B13/02 ,  G06F9/44 ,  G06N5/04 ,  G06N7/02 ,  G06N7/04

CPC classification number: G05B13/0275 ,  G06N7/04 ,  Y10S706/90

Abstract: An architecture for an electronic controller operated using fuzzy logic, including an input section with a plurality of inputs for analog or digital signals, a central control unit provided with memories wherein fuzzy logic membership functions are stored) and a defuzzyfier section has its input section composed of a plurality of fuzzyfiers arranged in parallel and independent of one another, each fuzzyfier including an analog input and a digital input for receving signals from external sensors, and digital outputs connected to the input of a corresponding read-only memory of the central unit to select the address of a memory word.Membership functions are stored and retrieved from a memory according to a method which simplifies addressing and reduces the number of required accesses.

Abstract translation: 一种用于使用模糊逻辑运行的电子控制器的架构，包括具有用于模拟或数字信号的多个输入的输入部分，设置有存储模糊逻辑隶属函数的存储器的中央控制单元），并且具有其输入部分的defuzzyfier部分组成 多个并联排列并且彼此独立的模糊器，每个模糊器包括用于从外部传感器接收信号的模拟输入和数字输入，以及连接到中央单元的对应的只读存储器的输入的数字输出， 选择一个内存字的地址。 根据简化寻址并减少所需访问次数的方法，从存储器存储和检索成员资格功能。

公开(公告)号：US5631177A

公开(公告)日：1997-05-20

申请号：US380725

申请日：1995-01-30

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L21/33

CPC classification number: H01L29/66712 ,  H01L21/823456 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/0847 ,  H01L29/42368

Abstract: A manufacturing process for an integrated circuit which includes at least one vertical-current-flow MOS transistor. The patterned photoresist which screens the body implant is also used to mask the etching of a nitride layer over a pad oxide. After the photoresist is cleared, the nitride pattern is transferred into the oxide, and the resulting oxide/nitride stack is used to mask the source implant. The nitride/oxide stack is then removed, the gate oxide is grown, and the gate layer is then deposited.

Abstract translation: 一种用于集成电路的制造方法，该集成电路包括至少一个垂直电流流量MOS晶体管。 屏蔽体植入物的图案化光致抗蚀剂还用于掩蔽衬垫氧化物上的氮化物层的蚀刻。 在光致抗蚀剂被清除之后，氮化物图案被转移到氧化物中，并且所得到的氧化物/氮化物堆叠用于掩蔽源植入物。 然后去除氮化物/氧化物堆叠，生长栅极氧化物，然后沉积栅极层。

公开(公告)号：US5629647A

公开(公告)日：1997-05-13

申请号：US493367

申请日：1995-06-21

Applicant: Andrea Fassina ,  Giovanni Avenia ,  Elia Pagani

Inventor： Andrea Fassina ,  Giovanni Avenia ,  Elia Pagani

IPC: G01R29/26 ,  G01R31/00 ,  G01R31/28 ,  H03F3/181 ,  H03G3/10 ,  H03F21/00

CPC classification number: G01R31/2825

Abstract: A method and device for measuring the switching noise of an audio amplifier by measuring the energy of the noise signal at the output of the audio amplifier as the amplifier is switched from one operating condition to another by a control signal, and after first weighing the energy according to the frequency and volume sensitivity of the human ear. The device comprises a control signal generator; an audio band filter connected to the output of the audio amplifier; a meter for measuring the power of the filtered signal; and an integrating element for calculating the energy of the filtered signal.

Abstract translation: 一种用于通过测量音频放大器的输出端的噪声信号的能量来测量音频放大器的开关噪声的方法和装置，当放大器通过控制信号从一个操作状态切换到另一个操作状态时，并且在首先称量能量 根据人耳的频率和体积灵敏度。 该装置包括控制信号发生器; 音频带滤波器连接到音频放大器的输出; 用于测量滤波信号的功率的仪表; 以及用于计算滤波信号的能量的积分元件。

公开(公告)号：US5627790A

公开(公告)日：1997-05-06

申请号：US408589

申请日：1995-03-22

Applicant: Carla M. Golla ,  Marco Olivo ,  Silvia Padoan

Inventor： Carla M. Golla ,  Marco Olivo ,  Silvia Padoan

IPC: G11C11/409 ,  G11C7/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28 ,  G11C7/02

CPC classification number: G11C7/14 ,  G11C16/28

Abstract: A device including a load connected by a selection circuit to a number of bit lines, and a load connected to a reference cell, for detecting the current in the selected bit line and in the reference cell. The load connected to the bit lines comprises a transistor, and the reference load comprises two current paths, each formed by one transistor. One of the two transistors is diode-connected, and the other is switchable by a switching network connected to the gate terminal of the respective transistor, for turning it off when only one reference current path is to be enabled, and for diode-connecting it when both the reference current paths are to be enabled.

Abstract translation: 一种包括通过选择电路连接到多个位线的负载的设备，以及连接到参考单元的负载，用于检测所选位线和参考单元中的电流。 连接到位线的负载包括晶体管，并且参考负载包括两个电流路径，每个由一个晶体管形成。 两个晶体管中的一个是二极管连接的，另一个晶体管可以由连接到相应晶体管的栅极端子的开关网络切换，以便在仅使能一个参考电流路径时将其关断，并且用于二极管连接 当两个参考电流路径都要使能时。

公开(公告)号：US5625309A

公开(公告)日：1997-04-29

申请号：US455856

申请日：1995-05-31

Applicant: Giona Fucili ,  Aldo Novelli

Inventor： Giona Fucili ,  Aldo Novelli

IPC: H03K3/037 ,  H03K3/289

CPC classification number: H03K3/037

Abstract: A bistable logic network of the sequential type, responsive to the edges of input signals, comprising first and second input SR flip-flops which are connected to an output SR flip-flop through two transfer and block logic gates.Each of said logic gates has two input terminals connected to the output terminal and to one input terminal of an input flip-flop.The output terminals of the output flip-flop are feedback connected to the other input terminals of the two input flip-flops.

Abstract translation: 响应于输入信号的边缘的顺序类型的双稳态逻辑网络包括通过两个传输和块逻辑门连接到输出SR触发器的第一和第二输入SR触发器。 每个所述逻辑门具有连接到输出端和输入触发器的一个输入端的两个输入端。 输出触发器的输出端子反馈连接到两个输入触发器的其他输入端子。

公开(公告)号：US5623216A

公开(公告)日：1997-04-22

申请号：US425000

申请日：1995-04-19

Applicant: Luigi Penza ,  Calogero Timineri

Inventor： Luigi Penza ,  Calogero Timineri

IPC: H03K17/16 ,  H03K17/687 ,  H03K17/695 ,  H03K19/003 ,  H03K19/0175

CPC classification number: H03K19/00361

Abstract: An output buffer current slew rate control integrated circuit includes an output buffer having first, MOS-type transistor means for supplying a current to a load impedance. Current generator means generate a constant current and are activated upon switching of an input signal of the output buffer. The current generator means drive a control input of the first transistor means for driving the first transistor means with a driving voltage having a slew rate determined by the constant current.

Abstract translation: 输出缓冲器电流转换速率控制集成电路包括具有第一MOS晶体管装置的输出缓冲器，用于向负载阻抗提供电流。 电流发生器意味着产生恒定电流并且在切换输出缓冲器的输入信号时被激活。 电流发生器装置驱动第一晶体管装置的控制输入，用于以具有由恒定电流确定的压摆率的驱动电压来驱动第一晶体管装置。

公开(公告)号：US5617055A

公开(公告)日：1997-04-01

申请号：US509304

申请日：1995-07-31

Applicant: Pierangelo Confalonieri ,  Germano Nicollini

Inventor： Pierangelo Confalonieri ,  Germano Nicollini

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H03K17/687 ,  H03K17/62

CPC classification number: H03K17/6872 ,  H03K2217/0018

Abstract: An electronic switch having a reduced body effect includes first and second switch terminals. A first transistor of a first type has a control terminal, a first substrate coupled to a first voltage level, and first and second drive terminals respectively coupled to the first and second switch terminals. A second transistor of a second type has a control terminal, a second substrate, a first drive terminal coupled to the second substrate and to the first switch terminal, and a second drive terminal. A third transistor of the second type has a control terminal, a third substrate, a first drive terminal coupled to the second drive terminal of the second transistor, and a second drive terminal coupled to the third substrate and to the second switch terminal. A fourth transistor of a first type has a control terminal, a fourth substrate, a first drive terminal coupled to the second drive terminal of the second transistor, and a second drive terminal coupled to the fourth substrate and a first voltage level.

Abstract translation: 具有减小的身体效应的电子开关包括第一和第二开关端子。 第一类型的第一晶体管具有控制端子，耦合到第一电压电平的第一衬底以及分别耦合到第一和第二开关端子的第一和第二驱动端子。 第二类型的第二晶体管具有控制端子，第二基板，耦合到第二基板和第一开关端子的第一驱动端子和第二驱动端子。 第二类型的第三晶体管具有控制端子，第三基板，耦合到第二晶体管的第二驱动端子的第一驱动端子和耦合到第三基板和第二开关端子的第二驱动端子。 第一类型的第四晶体管具有控制端子，第四衬底，耦合到第二晶体管的第二驱动端子的第一驱动端子和耦合到第四衬底的第二驱动端子和第一电压电平。

公开(公告)号：US5612641A

公开(公告)日：1997-03-18

申请号：US380309

申请日：1995-01-30

Applicant: Mauro L. Sali

Inventor： Mauro L. Sali

IPC: H03K3/356 ,  H03K17/00 ,  H03K17/22 ,  H03L7/00

CPC classification number: H03K3/356008 ,  H03K17/223 ,  H03K2217/0036

Abstract: A circuit for resetting initial conditions upon starting of an integrated circuit device has null current consumption under normal operating conditions. The circuit includes an input stage, which is a threshold circuit, and pilots through an input node an output stage which is a trigger circuit with hysteresis. The input node of the output stage is connected to ground through a condenser and is connected through a transistor to a connection node between a condenser and a diode connected transistor which are inserted between the power supply and ground. The gate terminal of the first transistor is grounded.

Abstract translation: 用于在集成电路器件启动时复位初始条件的电路在正常工作条件下具有零电流消耗。 该电路包括作为阈值电路的输入级，并且通过输入节点导出作为具有滞后的触发电路的输出级。 输出级的输入节点通过电容器连接到地，并通过晶体管连接到电容器和二极管连接的晶体管之间的连接节点，该晶体管插在电源和地之间。 第一晶体管的栅极端子接地。

公开(公告)号：US5605850A

公开(公告)日：1997-02-25

申请号：US471084

申请日：1995-06-06

Applicant: Flavio Villa

Inventor： Flavio Villa

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L21/265

CPC classification number: H01L29/1004 ,  Y10S148/01

Abstract: A low-noise PNP transistor comprising a cutoff region laterally surrounding the emitter region in the surface portion of the transistor. The cutoff region has such a conductivity is to practically turn off the surface portion of the transistor, so that the transistor operates mainly in the bulk portion. The cutoff region is formed by an N.sup.+ -type enriched base region arranged between the emitter region and the collector region.

Abstract translation: 一种低噪声PNP晶体管，包括横向围绕晶体管表面部分中的发射极区域的截止区域。 具有这种导电性的截止区域实际上关闭晶体管的表面部分，使得晶体管主要在本体部分中工作。 截止区域由布置在发射极区域和集电极区域之间的N +型富集基极区域形成。