公开(公告)号：US20030227401A1

公开(公告)日：2003-12-11

申请号：US10162324

申请日：2002-06-04

Applicant: Cirrus Logic, Inc.

Inventor： YuQing Yang ,  John Laurence Melanson

IPC: H03M003/00

CPC classification number: H03M3/368 ,  H03M3/424 ,  H03M3/452

Abstract: An integrator stage for use in a delta sigma modulator includes an operational amplifier, an integration capacitor coupling an output of the operational amplifier and a summing node at an input of the operational amplifier, and a feedback path. The feedback path includes first and second capacitors having first plates coupled electrically in common at a common plate node and switching circuitry for sampling selected reference voltages onto second plates of the capacitors during a sampling phase. The integrator stage further includes a switch for selectively coupling the common plate node and the summing node during an integration phase.

Abstract translation: 用于Δ-Σ调制器的积分器级包括运算放大器，耦合运算放大器的输出的积分电容器和运算放大器输入端的求和节点和反馈路径。 反馈路径包括第一和第二电容器，该第一和第二电容器具有在公共板节点处共同电耦合的第一板和用于在采样阶段期间将选定的参考电压采样到电容器的第二板上的开关电路。 积分器级还包括用于在积分阶段期间选​​择性地耦合公共板节点和求和节点的开关。

公开(公告)号：US06147522A

公开(公告)日：2000-11-14

申请号：US224390

申请日：1998-12-31

Applicant: Jason Powell Rhode ,  Vishnu Shankar Srinivasan ,  Eric Clay Gaalaas ,  Johann Guy Gaboriau

Inventor： Jason Powell Rhode ,  Vishnu Shankar Srinivasan ,  Eric Clay Gaalaas ,  Johann Guy Gaboriau

IPC: H03M3/02 ,  H03K27/02

CPC classification number: H03M3/368 ,  H03M3/502

Abstract: Circuitry for selectively sampling a reference voltage with a capacitor 403 includes a first switch 505a for selectively coupling capacitor 403 to a source of a first reference signal during a first operating phase and a second switch 505b for selectively coupling capacitor 403 to a source of a second reference signal during a second operating phase.

Abstract translation: 用电容器403选择性地对参考电压进行采样的电路包括：第一开关505a，用于在第一操作阶段期间将电容器403选择性地耦合到第一参考信号源;以及第二开关505b，用于将电容器403选择性地耦合到第二 参考信号在第二操作阶段。

公开(公告)号：US6133719A

公开(公告)日：2000-10-17

申请号：US418072

申请日：1999-10-14

Applicant: Prabir C. Maulik

Inventor： Prabir C. Maulik

IPC: G05F1/46 ,  G05F3/30 ,  G05F3/16 ,  G05F3/20

CPC classification number: G05F3/30 ,  G05F1/468 ,  Y10S323/901

Abstract: A technique for providing a start-up circuit for a bandgap reference. An amplifier configured in a differential arrangement as the bandgap reference. A start-up circuitry ensures that a second input node is maintained at a lower voltage than a first input node of the amplifier at start-up, when the output node corresponding to the second input side of the amplifier is also pulled low.

Abstract translation: 一种用于提供带隙基准的启动电路的技术。 放大器配置为差分布置作为带隙基准。 当与放大器的第二输入侧对应的输出节点也被拉低时，启动电路确保第二输入节点在启动时保持在比放大器的第一输入节点更低的电压。

公开(公告)号：US6118413A

公开(公告)日：2000-09-12

申请号：US136791

申请日：1998-08-19

Applicant: Vlad Bril ,  Rakesh Bindlish ,  Ken Fuiks ,  Robin Sungsoo Han ,  Sridhar Kotha ,  Alexander Julian Eglit

Inventor： Vlad Bril ,  Rakesh Bindlish ,  Ken Fuiks ,  Robin Sungsoo Han ,  Sridhar Kotha ,  Alexander Julian Eglit

IPC: G06F3/14 ,  G09G3/20 ,  G09G5/39 ,  G09G5/395 ,  G09G5/00

CPC classification number: G06F3/1431 ,  G09G2360/04 ,  G09G3/2051 ,  G09G5/39 ,  G09G5/395

Abstract: A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e.g., CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data "tag" (extra bit) is attached to each word or dword passing through the data path indicating the destination (e.g., CRT or LCD) of the video data. At the output of the data path, separate FIFOs (e.g., LCD and CRT) are provided to temporarily store video data. FIFO pointers are fed back to a sequence controller to drive data read cycles from display memory. The use of tags and FIFO pointer feedback allows two video displays to be driven at different data rates, allowing for independent resolution and refresh rates in each display.

Abstract translation: 一种用于控制具有独立的刷新率和像素分辨率的至少两个视频显示器的视频控制器。 在第一实施例中，在每个视频显示器（例如CRT和LCD）的视频控制器内提供两个单独的数据路径。 利用64位宽的DRAMS的带宽增加，可以在单独的读取周期中检索每个数据路径的数据。 每个数据通路可以在其自己的时钟频率下操作刷新率和像素分辨率的特性。 双数据路径实施例还降低了驱动这种双显示器所需的软件模型的复杂性。 在替代实施例中，可以在视频控制器内提供单个数据路径来驱动具有独立刷新率和像素分辨率的两个视频显示器的数据。 附加到通过指示视频数据的目的地（例如，CRT或LCD）的数据路径的每个字或双字的数据“标签”（额外位）。 在数据路径的输出端，提供分离的FIFO（例如LCD和CRT）以临时存储视频数据。 FIFO指针被反馈到序列控制器以从显示存储器驱动数据读取周期。 使用标签和FIFO指针反馈允许以不同的数据速率驱动两个视频显示器，允许在每个显示器中独立分辨率和刷新率。

公开(公告)号：US6111712A

公开(公告)日：2000-08-29

申请号：US36608

申请日：1998-03-06

Applicant: G. Diwakar Vishakhadatta ,  Jerrell P. Hein

Inventor： G. Diwakar Vishakhadatta ,  Jerrell P. Hein

IPC: G11B19/247 ,  G11B20/10 ,  G11B20/14 ,  H03L7/089 ,  H03L7/199 ,  H03L7/23 ,  G11B5/09

CPC classification number: H03L7/199 ,  G11B19/247 ,  G11B20/10009 ,  H03L7/23 ,  G11B20/1403 ,  H03L7/0891

Abstract: A system and method is provided to improve the jitter performance of high frequency synthesizers used in read/write channel circuits. The frequency synthesizer is implemented with multiple phase locked loops arranged in a cascaded fashion to increase the update rates at which the cascaded loops operate at for a given frequency resolution of the synthesizer. The cascaded or staged phase locked loops may be utilized for generating read, write, and servo clocks for a read/write channel circuit. The cascaded phase locked loops may also be arranged such that one or more stages are shared to generate the read, write or servo clocks.

Abstract translation: 提供了一种提高读/写通道电路中使用的高频合成器的抖动性能的系统和方法。 频率合成器由级联方式布置的多个锁相环实现，以增加级联环路在合成器的给定频率分辨率下工作的更新速率。 级联或分级锁相环可用于为读/写通道电路产生读，写和伺服时钟。 级联锁相环也可以被布置为使得一个或多个级被共享以产生读，写或伺服时钟。

公开(公告)号：US6111710A

公开(公告)日：2000-08-29

申请号：US882473

申请日：1997-06-25

Applicant: German S. Feyh ,  Sian She ,  William G. Bliss

Inventor： German S. Feyh ,  Sian She ,  William G. Bliss

IPC: G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  G11B5/035

CPC classification number: G11B20/10055 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/1426 ,  G11B5/012 ,  G11B5/09

Abstract: A sampled amplitude read channel is disclosed for reading data recorded on a disk storage medium by asynchronously sampling an analog read signal, equalizing the asynchronous sample values according to a desired partial response, and interpolating the equalized sample values to generate synchronous sample values substantially synchronized to a baud rate of the recorded data. The read channel further comprises a gain control circuit which generates a gain error for adjusting the amplitude of the analog read signal to a nominal value through a variable gain amplifier (VGA). During acquisition, the gain error is computed from the asynchronous sample values at the output of the sampling device in order to avoid the delay associated with the discrete equalizer filter and the timing recovery interpolation filter. This decreases the acquisition time and the corresponding length of the acquisition preamble, thereby reserving more area on the disk to record user data. After acquisition and while tracking the random user data, the gain control loop is reconfigured to generate the gain error according to using the synchronous, interpolated sample values output by the timing recovery circuit.

Abstract translation: 公开了采样幅度读通道，用于通过异步采样模拟读取信号来读取记录在磁盘存储介质上的数据，根据期望的部分响应对异步采样值进行均衡，并内插均衡的采样值，以生成基本上与 记录数据的波特率。 读通道还包括增益控制电路，其产生用于通过可变增益放大器（VGA）将模拟读取信号的幅度调整到标称值的增益误差。 在采集期间，从采样设备输出端的异步采样值计算增益误差，以避免与离散均衡滤波器和定时恢复插值滤波器相关的延迟。 这降低了采集前导码的采集时间和相应长度，从而在磁盘上保留更多的区域来记录用户数据。 在采集并跟踪随机用户数据之后，根据定时恢复电路输出的同步内插采样值重新配置增益控制环以产生增益误差。

公开(公告)号：US6101598A

公开(公告)日：2000-08-08

申请号：US970372

申请日：1997-11-14

Applicant: Miroslav Dokic ,  Raghunath Rao ,  Zheng Luo ,  Jeffrey Niehaus ,  James Divine

Inventor： Miroslav Dokic ,  Raghunath Rao ,  Zheng Luo ,  Jeffrey Niehaus ,  James Divine

IPC: G06F11/36 ,  G06F9/44

CPC classification number: G06F11/3656

Abstract: A method of operating a multiple processor device. A first word of a sequence of words is received in a register. A target processor is determined from the first word and the target processor is interrupted. An input ready bit is set and first word from in the register is read with the target processor. A number of words in the sequence to follow the first word determined from the first word. A word counter is set and the input ready bit is cleared with the target processor. The target processor is returned to main code execution.

Abstract translation: 一种操作多处理器设备的方法。 在一个寄存器中接收一个字序列的第一个字。 从第一个字确定目标处理器，并且目标处理器被中断。 输入就绪位被置位，并且用目标处理器读取寄存器中的第一个字。 序列中的多个单词遵循从第一个单词确定的第一个单词。 一个字计数器被设置并且输入就绪位被目标处理器清除。 目标处理器返回主代码执行。

公开(公告)号：US6069866A

公开(公告)日：2000-05-30

申请号：US956934

申请日：1997-10-23

Applicant: David M. Pietruszynski ,  Ion Constantin Tesu

Inventor： David M. Pietruszynski ,  Ion Constantin Tesu

IPC: G11B7/005 ,  G11B20/10 ,  H03G1/00 ,  G11B7/00

CPC classification number: H03G1/0088 ,  G11B20/10009 ,  G11B7/005

Abstract: A system and method for a data detection circuit is provided in which separate coarse gain amplifiers and fine gain amplifiers are utilized. The coarse gain amplifiers may include drain switching of transistors in order to modify the amplifier gain. More particularly, drain switching may be utilized to selectively switch in and out different differential input transistor pairs and/or different current sources. In this manner the gain of the amplifier may be adjusted to one of a variety of different coarse gain control levels. The coarse gain control provided allows for gain adjustments without significantly decreasing the bandwidth of the amplifier. In a preferred embodiment the system and method may be utilized for data detection circuits utilized in conjunction with optical disks.

Abstract translation: 提供了一种用于数据检测电路的系统和方法，其中使用单独的粗增益放大器和细增益放大器。 粗增益放大器可以包括晶体管的漏极切换以便改变放大器增益。 更具体地，可以利用漏极切换来选择性地切换和导出不同的差分输入晶体管对和/或不同的电流源。 以这种方式，可以将放大器的增益调整为各种不同的粗增益控制电平之一。 所提供的粗略增益控制允许增益调整，而不会显着降低放大器的带宽。 在优选实施例中，系统和方法可以用于与光盘结合使用的数据检测电路。

公开(公告)号：US6064638A

公开(公告)日：2000-05-16

申请号：US56288

申请日：1998-04-07

Applicant: James M. Graba

Inventor： James M. Graba

IPC: G11B7/00 ,  G11B7/085

CPC classification number: G11B7/08541 ,  G11B2007/0006 ,  G11B7/08529

Abstract: A track count estimator is provided for an optical storage device operating in either a CD-ROM mode or a DVD mode during a track seek. The track count estimator includes a state estimator to determine current and predicted estimates of the position and velocity of an optical pickup in the optical storage device according to the following equations:Current Estimate: X(k.vertline.k)=X(k.vertline.k-1)+K(Z(k)-X.sub.1 (k.vertline.k-1))Predicted Estimate: X(k+1.vertline.k)=Ad.multidot.X(k.vertline.k)The input to the state estimator can be selected from a CD-ROM signal (if the optical device is operating in a CD mode) or a DVD signal (if the optical device is operating in a DVD mode), the selected signal representing a half-track position error. An error signal is then generated which is processed separately in position and velocity portions of the state estimator. The output of the position portion is a track count signal which is used by the optical storage device to determine the position of the optical pickup relative to a destination track. Track counting with the present invention provides higher resolution than conventional methods and is less prone to noise, dropouts and defects, thereby decreasing overall seek times while increasing seek accuracy.

Abstract translation: 为在轨道搜索期间以CD-ROM模式或DVD模式操作的光存储设备提供轨道计数估计器。 轨道计数估计器包括状态估计器，用于根据以下等式确定光学存储设备中的光学拾取器的位置和速度的当前和预测的估计：电流估计：+ E，cir X + EE（k | k）= + E，cir X + EE（k | k-1）+ K（Z（k） - + E，cir X + EE 1（k | k-1））预测估计：+ E，cir X + EE +1 | k）= Adx + E，cir X + EE（k | k）可以从CD-ROM信号（如果光学设备以CD模式操作）或DVD信号选择状态估计器的输入 （如果光学设备以DVD模式工作），所选择的信号表示半径位置误差。 然后产生在状态估计器的位置和速度部分单独处理的误差信号。 位置部分的输出是由光学存储装置用于确定光学拾取器相对于目的地轨道的位置的轨道计数信号。 利用本发明的跟踪计数提供比常规方法更高的分辨率，并且更不容易产生噪声，丢失和缺陷，从而在增加寻道精度的同时减少总体寻道时间。

公开(公告)号：US6047395A

公开(公告)日：2000-04-04

申请号：US16563

申请日：1998-01-30

Applicant: Christopher P. Zook

Inventor： Christopher P. Zook

IPC: G11B20/18 ,  H03M13/15 ,  H03M13/29 ,  H03M13/00

CPC classification number: H03M13/154 ,  G11B20/1833 ,  H03M13/158 ,  H03M13/29 ,  H03M13/2909 ,  H03M13/2924 ,  H03M13/293 ,  G11B20/18

Abstract: An error correction processor is disclosed for correcting errors in binary data read from a disk storage medium, wherein the binary data comprises a first and second set of intersecting ECC codewords of a multi-dimensional codeword. The error correction processor comprises a data buffer for storing the ECC codewords read from the disk storage medium; a syndrome generator for generating ECC syndromes in response to a codeword in the second set; an error-locator polynomial generator for generating an error locator polynomial .sigma.(x) in response to the ECC syndromes; a selector for selecting between the error-locator polynomial .sigma.(x) and an erasure polynomial .sigma.(x).sub.EP, wherein:(i) the erasure polynomial .sigma.(x).sub.EP is generated while processing the first set codewords; and(ii) the erasure polynomial .sigma.(x).sub.EP is used to correct at least two codewords in the second set; andan error corrector for generating correction values in response to either the error-locator polynomial .sigma.(x) or the erasure polynomial .sigma.(x).sub.EP output by the selector, the correction values for correcting errors in the codeword in the second set.

Abstract translation: 公开了一种用于校正从盘存储介质读取的二进制数据中的错误的纠错处理器，其中二进制数据包括多维码字的第一和第二组相交ECC码字。 纠错处理器包括用于存储从盘存储介质读取的ECC码字的数据缓冲器; 用于响应于第二组中的码字生成ECC综合征的校正子发生器; 一个误差定位器多项式发生器，用于响应ECC校验子产生误差定位多项式sigma（x）; 用于在误差定位多项式sigma（x）和擦除多项式sigma（x）EP之间进行选择的选择器，其中：（i）在处理第一集合码字时产生擦除多项式sigma（x）EP; 和（ii）擦除多项式sigma（x）EP用于校正第二组中的至少两个码字; 以及用于响应于由选择器输出的误差定位多项式sigma（x）或擦除多项式sigma（x）EP）产生校正值的纠错器，用于校正第二组中码字中的错误的校正值。