中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

365 records (took 0.079 seconds)

    Semiconductor devices with self-aligned contacts and low-k spacers
    252.
    发明授权
    Semiconductor devices with self-aligned contacts and low-k spacers 有权
    具有自对准触点和低k间隔物的半导体器件

    公开(公告)号：US09543426B2

    公开(公告)日：2017-01-10

    申请号：US13957587

    申请日：2013-08-02

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC: H01L29/78 ,  H01L29/66 ,  H01L21/768

    CPC classification number: H01L29/78 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

    Abstract: One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.

    Abstract translation: 本文公开的一种说明性方法包括去除牺牲侧壁间隔物的一部分，从而暴露牺牲栅电极的侧壁的至少一部分，并在牺牲栅电极的暴露的侧壁上形成衬垫层。 在该示例中，该方法还包括在衬垫层之上形成牺牲间隙填充材料，暴露和去除牺牲栅极电极，从而限定由衬里层横向限定的栅极腔，形成替代栅极结构，去除牺牲层 间隙填充材料并形成邻近衬层的低k侧壁间隔物。 还公开了一种器件，其包括栅极覆盖层，位于栅极绝缘层的两个直立部分中的每一个上的氮化硅或氮氧化硅层，以及位于氮化硅或氮氧化硅层上的低k侧壁间隔物。

    Methods of forming different FinFET devices having different fin heights and an integrated circuit product containing such devices
    253.
    发明授权
    Methods of forming different FinFET devices having different fin heights and an integrated circuit product containing such devices 有权
    形成具有不同翅片高度的不同FinFET器件的方法和包含这种器件的集成电路产品

    公开(公告)号：US09530775B2

    公开(公告)日：2016-12-27

    申请号：US13916013

    申请日：2013-06-12

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/66795 ,  H01L29/7851

    Abstract: One illustrative method disclosed herein includes forming a plurality of trenches in a plurality of active regions of a substrate that defines at least a first plurality of fins and a second plurality of fins for first and second FinFET devices, respectively, forming liner materials adjacent to the first and second plurality of fins, wherein the liner materials adjacent the first fins and the second fins have a different thickness. The method also includes removing insulating material to expose portions of the liner materials, performing an etching process to remove portions of the liner materials so as to expose at least one fin in the first plurality of fins to a first height and at least one of the second plurality of fins to a second height that is different from the first height.

    Abstract translation: 本文公开的一种说明性方法包括在衬底的多个有源区域中形成多个沟槽，所述多个有源区域分别限定用于第一和第二FinFET器件的至少第一多个鳍片和第二多个鳍片，以形成邻近 第一和第二多个翅片，其中与第一鳍片和第二鳍片相邻的衬垫材料具有不同的厚度。 该方法还包括去除绝缘材料以暴露衬里材料的部分，执行蚀刻工艺以去除衬里材料的部分，以便将第一组多个鳍中的至少一个翅片暴露于第一高度，并且将至少一个 第二多个翅片到与第一高度不同的第二高度。

    Semiconductor structures with stacked non-planar field effect transistors and methods of forming the structures
    255.
    发明授权
    Semiconductor structures with stacked non-planar field effect transistors and methods of forming the structures 有权
    具有堆叠非平面场效应晶体管的半导体结构和形成结构的方法

    公开(公告)号：US09472558B1

    公开(公告)日：2016-10-18

    申请号：US14940499

    申请日：2015-11-13

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Carl Radens ,  Robert C. Wong

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L27/11 ,  H01L23/528 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06

    CPC classification number: H01L27/1116 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0688 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

    Abstract: Disclosed are semiconductor structures and methods of forming them. The structures include field effect transistors (FETs) with different type conductivities in different levels, respectively, of the same fin, wherein the numbers of FETs in the different levels are different. Specifically, in a fin, a first semiconductor layer has source/drain and channel regions for a first and a second transistor and a second semiconductor layer has source/drain and channel regions for a third transistor with a different type conductivity than first and second transistors. A gate is on the top surface and sides of the first semiconductor layer at the channel region of the first transistor. Another gate has a lower portion on the sides of the first semiconductor layer at the channel region of the second transistor and an upper portion on the top surface and sides of the second semiconductor layer at the channel region of the third transistor.

    Abstract translation: 公开了半导体结构及其形成方法。 该结构分别包括具有不同级别的不同类型电导率的场效应晶体管（FET），其中不同级别的FET的数量是不同的。 具体地，在散热片中，第一半导体层具有用于第一和第二晶体管的源极/漏极和沟道区，并且第二半导体层具有用于具有与第一和第二晶体管不同的导电类型的第三晶体管的源极/漏极和沟道区 。 栅极位于第一晶体管的沟道区的第一半导体层的顶表面和侧面上。 另一个栅极在第二晶体管的沟道区域处具有在第一半导体层的侧面上的下部，在第三晶体管的沟道区域处的第二半导体层的顶部表面和侧面上的上部。

    Uniform depth fin trench formation
    256.
    发明授权
    Uniform depth fin trench formation 有权
    均匀深度鳍状沟形成

    公开(公告)号：US09472460B1

    公开(公告)日：2016-10-18

    申请号：US15007494

    申请日：2016-01-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Alexander Reznicek ,  Kangguo Cheng ,  Ali Khakifirooz ,  Dominic J. Schepis ,  Pouya Hashemi

    IPC: H01L21/8234 ,  H01L29/06 ,  H01L21/228 ,  H01L21/3065 ,  H01L21/02

    CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L29/785

    Abstract: Methods for forming substantially uniform depth trenches and/or semiconductor fins from the trenches are disclosed. Embodiments of the method may include depositing a germanium including layer over a substrate, the substrate including a plurality of sacrificial semiconductor fins, each pair of sacrificial semiconductor fins separated by a sacrificial pillar. Germanium is diffused from the germanium including layer into the plurality of sacrificial semiconductor fins to a defined uniform depth. The germanium including layer is removed, and the plurality of sacrificial semiconductor fins are etched to the defined uniform depth and selective to the substrate, creating a plurality of trenches having a substantially uniform depth. The trenches can be used to epitaxial grow semiconductor fins having substantially uniform height.

    Abstract translation: 公开了从沟槽形成基本均匀的深度沟槽和/或半导体鳍片的方法。 该方法的实施例可以包括在衬底上沉积包含锗的层，衬底包括多个牺牲半导体鳍片，每对牺牲半导体鳍片由牺牲柱分隔开。 锗从含锗层扩散到多个牺牲半导体鳍片到规定的均匀深度。 去除含锗层，并且将多个牺牲半导体散热片蚀刻到规定的均匀深度并对衬底有选择性，从而产生具有基本均匀深度的多个沟槽。 沟槽可用于外延生长具有基本均匀的高度的半导体鳍片。

    Electrically controlled optical fuse and method of fabrication
    258.
    发明授权
    Electrically controlled optical fuse and method of fabrication 有权
    电控光熔丝及其制造方法

    公开(公告)号：US09417501B2

    公开(公告)日：2016-08-16

    申请号：US14529243

    申请日：2014-10-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Kangguo Cheng ,  Raghavasimhan Sreenivasan

    IPC: G02B6/42 ,  G02F1/17 ,  G02B6/10 ,  G02B26/02 ,  H01L31/18

    CPC classification number: G02F1/17 ,  G02B6/10 ,  G02B26/02 ,  H01L31/18

    Abstract: Embodiments of the present invention provide an electrically controlled optical fuse. The optical fuse is activated electronically instead of by the light source itself. An applied voltage causes the fuse temperature to rise, which induces a transformation of a phase changing material from transparent to opaque. A gettering layer absorbs excess atoms released during the transformation.

    Abstract translation: 本发明的实施例提供一种电控光熔丝。 光学保险丝以电子方式激活而不是由光源本身激活。 施加的电压导致熔丝温度升高，这导致相变材料从透明变为不透明。 吸收层吸收在转化期间释放的多余原子。

    Suspended ring-shaped nanowire structure
    259.
    发明授权
    Suspended ring-shaped nanowire structure 有权
    悬挂环形纳米线结构

    公开(公告)号：US09406790B2

    公开(公告)日：2016-08-02

    申请号：US14505018

    申请日：2014-10-02

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kangguo Cheng ,  James J. Demarest ,  Balasubramanian S. Haran

    IPC: H01L29/66 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06 ,  H01L21/308 ,  H01L29/423 ,  H01L29/786 ,  B82Y40/00 ,  H01L21/02 ,  B82Y99/00

    CPC classification number: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3086 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/78696 ,  Y10S977/938

    Abstract: A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.

    Abstract translation: 具有垂直平面的心轴形成在单晶半导体层上。 通过选择性外延在单晶半导体层上形成外延半导体层。 围绕心轴的上部形成第一间隔件。 使用第一间隔物作为蚀刻掩模，外延半导体层垂直凹入。 在第一间隔物的侧壁和外延半导体层的垂直部分上形成第二间隔物。 从外延半导体层的垂直部分的下方蚀刻外延半导体层的水平底部部分，以形成附接到心轴的悬挂的环形半导体鳍片。 使用覆盖心轴的两个端部的图案化掩模层来蚀刻心轴的中心部分。 提供悬挂的半导体鳍片，其由一对支撑结构悬挂。

Patent Agency Ranking