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    Semiconductor devices and related methods
    251.
    发明授权
    Semiconductor devices and related methods 有权

    公开(公告)号：US10700279B2

    公开(公告)日：2020-06-30

    申请号：US16200969

    申请日：2018-11-27

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal R. Parekh

    IPC: H01L45/00 ,  H01L43/02 ,  H01L27/24 ,  H01L21/033 ,  H01L21/768 ,  H01L43/08 ,  H01L43/12

    Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

    Integrated Structures
    255.
    发明申请
    Integrated Structures 审中-公开

    公开(公告)号：US20170317098A1

    公开(公告)日：2017-11-02

    申请号：US15651719

    申请日：2017-07-17

    Applicant: Micron Technology, Inc.

    Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

    IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/76

    CPC classification number: H01L27/11582 ,  H01L29/66666 ,  H01L29/76 ,  H01L29/7827

    Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

    Integrated Structures
    257.
    发明申请
    Integrated Structures 有权
    综合结构

    公开(公告)号：US20170054036A1

    公开(公告)日：2017-02-23

    申请号：US14830517

    申请日：2015-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

    IPC: H01L29/792 ,  H01L29/423 ,  H01L27/115

    CPC classification number: H01L27/11582 ,  H01L29/66666 ,  H01L29/76

    Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

    Abstract translation: 一些实施例包括具有导电材料的集成结构，导电材料上的选择器件栅极材料以及选择器件栅极材料上的垂直堆叠的导电电平。 垂直延伸的单片通道材料与选择器件栅极材料和导电电平相邻。 单片通道材料包含与选择器件栅极材料相邻的下部段和邻近导电层的上段。 第一垂直延伸区域在单片通道材料的下段和选择器件栅极材料之间。 第一垂直延伸区域包含第一材料。 第二垂直延伸区域位于单片通道材料的上部段和导电层之间。 第二垂直延伸区域包含与第一材料的组成不同的材料。

    Arrays of memory cells and methods of forming an array of memory cells
    258.
    发明授权
    Arrays of memory cells and methods of forming an array of memory cells 有权
    存储单元阵列和形成存储单元阵列的方法

    公开(公告)号：US09553262B2

    公开(公告)日：2017-01-24

    申请号：US13761570

    申请日：2013-02-07

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal R. Parekh

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L27/2463 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

    Abstract: An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.

    Abstract translation: 存储单元阵列包括具有导电掺杂半导体材料的掩埋访问线。 支柱向外延伸并沿着掩埋的进入管线间隔开。 支柱分别包括一个记忆单元。 外部接入线在柱子和埋入式接入线路的正上方。 外部接入线路比埋入式接入线路的导电性高。 多个导电通孔沿着并且电耦合埋入和外部接入线路中的各个对间隔开。 多个支柱在沿对之间的通孔的紧邻之间。 导电金属材料直接抵靠埋入式接入线路的顶部，并沿独立的埋入式接入线路在支柱之间延伸。 公开了包括方法的其它实施例。

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