公开(公告)号：US20160212456A1

公开(公告)日：2016-07-21

申请号：US14598299

申请日：2015-01-16

Applicant: ANALOG DEVICES GLOBAL

Inventor： Chris W. Bohm ,  Narsimh Dilip Kamath

IPC: H04N21/236 ,  B60R11/04 ,  H04N21/234 ,  H04N21/4223 ,  H04N21/2365 ,  H04N21/414 ,  H04H20/62

CPC classification number: H04N21/23602 ,  B60R11/04 ,  G06F13/38 ,  G06F13/4291 ,  H04H20/62 ,  H04L1/0057 ,  H04L25/4904 ,  H04L25/493 ,  H04N7/18 ,  H04N7/181 ,  H04N21/23406 ,  H04N21/2365 ,  H04N21/41422 ,  H04N21/4223 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system for receiving at least two data streams and providing a single input data stream to a MIPI's CSI Tx is disclosed. The two received data streams are written into respective data buffers. The system includes a control logic configured to control reading of data stored in the buffers to a multiplexer, the read-side clock being a multiple of a frequency of a fixed frequency clock. The control logic is further configured to control the multiplexer to combine data read from each buffer that corresponds to a complete unit of data into a separate portion and multiplex the separate portions into the input data stream. In this manner, two data streams may be transmitted using a single CSI Tx. When the two data streams are received by the system from an APIX interface, the system provides a bridge between the APIX interface and MIPI's CSI Tx.

Abstract translation: 公开了一种用于接收至少两个数据流并向MIPI的CSI Tx提供单个输入数据流的系统。 两个接收的数据流被写入相应的数据缓冲器。 该系统包括控制逻辑，其被配置为控制将存储在缓冲器中的数据读取到多路复用器，读侧时钟是固定频率时钟频率的倍数。 控制逻辑还被配置为控制多路复用器将从与完整数据单元对应的每个缓冲器读取的数据组合成单独的部分，并将分离的部分复用到输入数据流中。 以这种方式，可以使用单个CSI Tx发送两个数据流。 当系统从APIX接口接收到两个数据流时，系统提供了APIX接口和MIPI的CSI Tx之间的桥梁。

公开(公告)号：US09391628B1

公开(公告)日：2016-07-12

申请号：US14967880

申请日：2015-12-14

Applicant: ANALOG DEVICES GLOBAL

Inventor： Colin G. Lyden ,  Pasquale Delizia ,  Sanjay Rajasekhar ,  Yogesh Jayarman Sharma ,  Arthur J. Kalb ,  Marvin L. Shu ,  Gerard Mora-Puchalt ,  Roberto S. Maurino

IPC: H03M1/38 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12

CPC classification number: H03M1/1245 ,  G11C27/026

Abstract: An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.

Abstract translation: 模数转换器（ADC）的输入级包括至少一个用于采集相位中的输入信号的采样电容器（SC），用于向SC提供输入信号的电容增益放大器（CGA）以及带宽控制装置 。 带宽控制装置被配置为确保SC在获取阶段的第一部分期间具有第一带宽，并且在所述获取阶段的后续，第二部分期间具有第二带宽，第二带宽小于第一带宽。 以这种方式，首先，以更高的第一带宽对输入信号进行采样，从而可利用使用高带宽CGA来最小化SC上的稳定误差，并且接下来在相同获取阶段的第二部分期间 ，输入信号以较低，第二带宽进行采样，有利于降低使用高带宽CGA导致的噪声。

公开(公告)号：US09391578B2

公开(公告)日：2016-07-12

申请号：US14302223

申请日：2014-06-11

Applicant: ANALOG DEVICES GLOBAL

Inventor： Muhammad Kalimuddin Khan ,  Michael J. Deeney ,  Niall Kevin Kearney ,  Kenneth J. Mulvaney ,  Shane A. O'Mahony

IPC: H04B1/38 ,  H03G3/30 ,  H04B1/30

CPC classification number: H03G3/3052 ,  H03G3/3068 ,  H04B1/30 ,  H04B2001/305

Abstract: An LIF receiver includes a receiver path comprising: a mixer for mixing a received RF signal with a local oscillator signal to provide an IF signal at a lower frequency than the received RF signal, a bandpass filter for filtering the IF signal, a PGA for amplifying the filtered IF signal, an ADC for converting the amplified filtered IF signal to a digital signal, a converter for converting the digital signal to a baseband digital signal, and an AGC for setting a gain of the PGA in response to a magnitude of the received RF signal. A programmable DC signal source injects a programmed DC offset signal into the amplified filtered IF signal converted by the ADC, and a signal sensor, operatively connected to the receiver path after the PGA, determines a polarity of PGA signal output for a programmed DC offset signal. A controller determines a programmed DC offset signal minimizing a magnitude of the baseband signal in the absence of a received RF signal for at least one gain setting of the PGA.

Abstract translation: LIF接收机包括：接收机路径，包括：混合器，用于将接收到的RF信号与本地振荡器信号混合，以提供比所接收的RF信号低的频率的IF信号;滤波IF信号的带通滤波器;用于放大的PGA 经滤波的IF信号，用于将放大的滤波IF信号转换为数字信号的ADC，用于将数字信号转换为基带数字信号的转换器，以及响应于接收到的幅度的设定PGA的增益的AGC 射频信号。 可编程DC信号源将经编程的DC偏移信号注入由ADC转换的经放大的经滤波的IF信号中，并且在PGA之后可操作地连接到接收器路径的信号传感器确定编程的DC偏移信号的PGA信号输出的极性 。 控制器确定在没有接收的RF信号的情况下使PGA的至少一个增益设置最小化基带信号幅度的编程的DC偏移信号。

公开(公告)号：US20160197563A1

公开(公告)日：2016-07-07

申请号：US14912514

申请日：2014-08-22

Applicant: ANALOG DEVICES GLOBAL

Inventor： Jonathan Ephraim David Hurwitz ,  Seyed Amir Ali Danesh ,  William Michael James Holland

IPC: H02M7/217

CPC classification number: H02M7/217

Abstract: The present invention relates to power conversion apparatus (40) configured to receive a high voltage alternating current (AC) signal at an input (42, 44) and to provide in dependence thereon a low voltage direct current (DC) signal from an output stage (58, 60). The power conversion apparatus (40) comprises a main path comprising a high voltage capacitor (46) in series with the input. The power conversion apparatus (40) also comprises a first path operative to carry current carried by the main path in at least one of a positive going part and a negative going part of the high voltage alternating current signal and a second path operative to carry current carried by the main path in a positive going part and a negative going part of the high voltage alternating current signal. The power conversion apparatus further comprises first and second switches (52, 54) which are operative to determine when a respective one of the first and second paths carries current. In the power conversion apparatus, the output stage (58, 60) receives current flowing in the first path and at least one of the first and second switches (52, 54) is operable in dependence on a control signal derived from the low voltage direct current signal.

Abstract translation: 本发明涉及一种被配置为在输入端（42,44）处接收高压交流（AC）信号并根据其提供来自输出级的低电压直流（DC）信号的功率转换装置（40） （58,60）。 电力转换装置（40）包括与输入串联的高压电容器（46）的主路径。 功率转换装置（40）还包括第一路径，其操作以在高压交流信号的正向部分和负向部分中的至少一个中承载由主路径承载的电流，以及第二路径，其操作以承载电流 主路径承载在高压交流信号的正向部分和负向部分。 电力转换装置还包括第一和第二开关（52,54），其可操作以确定第一和第二路径中的相应一个何时承载电流。 在功率转换装置中，输出级（58,60）接收在第一路径中流动的电流，并且第一和第二开关（52,54）中的至少一个可根据从低电压直接导出的控制信号 电流信号。

公开(公告)号：US09385673B2

公开(公告)日：2016-07-05

申请号：US14321426

申请日：2014-07-01

Applicant: ANALOG DEVICES GLOBAL

Inventor： Fazil Ahmad ,  Gavin P. Cosgrave

IPC: H03F1/02 ,  H03F3/45 ,  H03F1/32

CPC classification number: H03F3/45977 ,  H03F1/3211 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2200/375 ,  H03F2203/45138 ,  H03F2203/45522

Abstract: Aspects of this disclosure relate to compensating for a relatively large offset in a signal generated by a sensor, such as a pressure sensor and/or a resistive bridge based sensor. Such offset compensation can include applying an offset correction signal generated by a configurable voltage reference, such as a voltage mode digital-to-analog converter (DAC), to an input of an amplifier included in an instrumentation amplifier to compensate for the offset of the signal generated by the sensor.

Abstract translation: 本公开的方面涉及补偿由传感器（例如压力传感器和/或基于电阻桥的传感器）产生的信号中的相对大的偏移。 这样的偏移补偿可以包括将由诸如电压模式数模转换器（DAC）的可配置电压基准产生的偏移校正信号应用于包括在仪表放大器中的放大器的输入，以补偿 由传感器产生的信号。

公开(公告)号：US20160173272A1

公开(公告)日：2016-06-16

申请号：US14568818

申请日：2014-12-12

Applicant: Analog Devices Global

Inventor： Muhammad Kalimuddin Khan ,  Kenneth J. Mulvaney

IPC: H04L7/04

CPC classification number: H04L7/04 ,  H03L7/00 ,  H03L7/07 ,  H04L7/033 ,  H04L27/00

Abstract: A clock and data recovery (CDR) system may use one or more clock signals in sync with recovered data rate. By accumulating a dithering tuning counter value at a data oversampling rate, a plurality of single bit signals at multiples of the recovered data rate and in sync with the recovered data rate can be accurately generated while utilizing the full range of the accumulator. This plurality of clock signals can be used in various modules in the CDR system and other modules in a transceiver system incorporating the CDR system.

Abstract translation: 时钟和数据恢复（CDR）系统可以使用与恢复的数据速率同步的一个或多个时钟信号。 通过以数据过采样率累积抖动调谐计数器值，可以在利用累加器的全范围的同时，以恢复的数据速率的倍数与恢复的数据速率同步的多个单比特信号被精确地产生。 该多个时钟信号可以用在CDR系统中的各种模块中以及包含CDR系统的收发机系统中的其他模块中。

公开(公告)号：US20160133701A1

公开(公告)日：2016-05-12

申请号：US14539593

申请日：2014-11-12

Applicant: ANALOG DEVICES GLOBAL

Inventor： Breandan Pol Og O hAnnaidh ,  Seamus Paul Whiston ,  Edward John Coyne ,  William Allan Lane ,  Donal Peter McAuliffe

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0692 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/7835 ,  H01L29/808

Abstract: A transistor is provided in which an elongate drain region has end portions formed in parts of the transistor where features of the transistor structure have been modified or omitted. These structures lessen the current flow or electric field gradients at the end portions of the drain. This provides a transistor that has improved on-state breakdown performance without sacrificing off state breakdown performance.

Abstract translation: 提供一种晶体管，其中细长的漏极区域具有形成在晶体管的部分中的端部，其晶体管结构的特征已被修改或省略。 这些结构减少了漏极端部处的电流或电场梯度。 这提供了具有改善的导通状态击穿性能而不牺牲关断状态击穿性能的晶体管。

公开(公告)号：US20160118959A1

公开(公告)日：2016-04-28

申请号：US14719241

申请日：2015-05-21

Applicant: Analog Devices Global

Inventor： Yusuf Alperen Atesal ,  Peter J. Katzin

IPC: H03H11/24

CPC classification number: H03H11/245 ,  H03H7/25

Abstract: Apparatus and methods for reducing glitches in digital step attenuators are disclosed. By configuring a multi-bit DSA such that an attenuation control block changes a plurality of control signals in a manner sequencing individual switches of the DSA, glitches can be reduced and RF signal behavior can be enhanced. The sequence, based upon a unit time delay, causes the transient attenuation value to be bounded between a minimum and maximum and can improve settling time.

Abstract translation: 公开了用于减少数字步进衰减器中的毛刺的装置和方法。 通过配置多比特DSA，使得衰减控制块以对DSA的各个交换机进行排序的方式改变多个控制信号，可以减少毛刺并且可以提高RF信号行为。 该序列基于单位时间延迟，导致瞬态衰减值在最小和最大值之间的界限，并可以提高建立时间。

公开(公告)号：US09325337B1

公开(公告)日：2016-04-26

申请号：US14593591

申请日：2015-01-09

Applicant: ANALOG DEVICES GLOBAL

Inventor： Dennis A. Dempsey

IPC: H03M1/10 ,  H03M1/66

CPC classification number: H03M1/109 ,  H03M1/1038 ,  H03M1/66

Abstract: In contrast to some existing techniques, a calibration technique compares multiple outputs which may be, for example, successive or different outputs from the digital-to-analog converter (DAC) in an analog environment and determines differences between at least two outputs in an analog environment. A feedback signal is provided in the digital environment to provide an internal or self-calibration regime. The digital feedback signal is provided to a digital signal processing (DSP) component of the calibration circuitry which uses the feedback signal to determine appropriate input codes to provide to the DAC. The same DAC can be used for both signal generation and feedback DAC purposes, and this provides a self-calibration of the DAC performance which is typically related to the integral non-linearity (INL) characteristics of the DAC transfer function.

Abstract translation: 与一些现有技术相比，校准技术比较多个输出，其可以是例如模拟环境中的数模转换器（DAC）的连续或不同的输出，并且确定模拟的至少两个输出之间的差异 环境。 在数字环境中提供反馈信号以提供内部或自校准方式。 将数字反馈信号提供给校准电路的数字信号处理（DSP）部件，其使用反馈信号来确定适当的输入代码以提供给DAC。 相同的DAC可用于信号发生和反馈DAC用途，并且这提供了DAC性能的自校准，其通常与DAC传递函数的积分非线性（INL）特性相关。

公开(公告)号：US20160093579A1

公开(公告)日：2016-03-31

申请号：US14502363

申请日：2014-09-30

Applicant: Analog Devices Global

Inventor： Yusuf Alperen Atesal ,  Turusan Kolcuoglu

IPC: H01L23/66 ,  H01L27/02 ,  H04B3/32 ,  H01L23/60 ,  H01L23/64 ,  H01L23/00 ,  H01L23/50

CPC classification number: H01L23/66 ,  H01L23/50 ,  H01L23/60 ,  H01L23/64 ,  H01L23/642 ,  H01L23/647 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0248 ,  H01L2223/6611 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/45014 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/1207 ,  H01L2924/1421 ,  H04B3/32 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: Aspects of this disclosure relate to a termination circuit configured to mitigate crosstalk from a radio frequency (RF) input/output (I/O) path to a second I/O path, such as a digital I/O path. Such crosstalk can be due to coupling between adjacent bond wires, for example. The termination circuit can include a low impedance loss path, such as a series RC shunt circuit. According to certain embodiments, an electrostatic discharge (ESD) protection circuit can be in parallel with the termination circuit.

Abstract translation: 本公开的方面涉及被配置为减轻从射频（RF）输入/输出（I / O）路径到诸如数字I / O路径的第二I / O路径的串扰的终端电路。 这种串扰可能是由于例如相邻接合线之间的耦合。 终端电路可以包括低阻抗损耗路径，例如串联RC分流电路。 根据某些实施例，静电放电（ESD）保护电路可以与终端电路并联。