公开(公告)号：US20230420512A1

公开(公告)日：2023-12-28

申请号：US17850778

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Sukru YEMENICIOGLU ,  Xinning WANG ,  Nischal ARKALI RADHAKRISHNA ,  Leonard P. GULER ,  Mauro J. KOBRINSKY ,  June CHOI ,  Pratik PATEL ,  Tahir GHANI

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L23/48 ,  H01L29/775

CPC classification number: H01L29/0673 ,  H01L27/0886 ,  H01L29/775 ,  H01L29/78696 ,  H01L23/481 ,  H01L29/42392

Abstract: Integrated circuit structures having backside power staple are described. In an example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts is extending over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A front-side metal routing layer is extending over one or more of the plurality of gate lines, and over and coupled to one or more of the plurality of trench contacts. A backside metal routing layer is extending beneath the one or more of the plurality of gate lines and the one or more of the plurality of trench contacts, the backside metal routing layer parallel and overlapping with the front-side metal routing layer. A conductive feedthrough structure couples the backside metal routing layer to the front-side metal routing layer.

公开(公告)号：US20230420360A1

公开(公告)日：2023-12-28

申请号：US17850779

申请日：2022-06-27

Applicant: INTEL CORPORATION

Inventor： Mohit HARAN ,  Sukru YEMENICIOGLU ,  Pratik PATEL ,  Charles H. WALLACE ,  Leonard P. GULER ,  Conor P. PULS ,  Makram ABD EL QADER ,  Tahir GHANI

IPC: H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

CPC classification number: H01L23/5226 ,  H01L27/0207 ,  H01L2027/11875 ,  H01L27/11807 ,  H01L23/5283

Abstract: Integrated circuit structures having recessed self-aligned deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

公开(公告)号：US20230317148A1

公开(公告)日：2023-10-05

申请号：US17710942

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Clifford ONG ,  Leonard P. GULER ,  Smita SHRIDHARAN ,  Zheng GUO ,  Charles H. WALLACE ,  Eric A. KARL ,  Mauro J. KOBRINSKY ,  Shem O. OGADHOH ,  Tahir GHANI

IPC: G11C11/417 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L27/1104

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BM0) and a backside of an epitaxial structure, as well as electrical connection structures that electrically couple the BM0 to a front side of an epitaxial structure. Other embodiments may be described and/or claimed.

公开(公告)号：US20230290843A1

公开(公告)日：2023-09-14

申请号：US17693124

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Chanaka D. MUNASINGHE ,  Charles H. WALLACE ,  Tahir GHANI ,  Krishna GANESAN

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088

CPC classification number: H01L29/41783 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/401 ,  H01L27/088 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/413

Abstract: Contact over active gate (COAG) structures with uniform and conformal gate insulating cap layers, and methods of fabricating contact over active gate (COAG) structures using uniform and conformal gate insulating cap layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is laterally spaced apart from the gate structure. A dielectric spacer is laterally between the gate structure and the epitaxial source or drain structure, the dielectric spacer having an uppermost surface below an uppermost surface of the gate structure. A gate insulating cap layer is on the uppermost surface of the gate structure and along upper portions of sides of the gate structure, the gate insulating cap layer distinct from the dielectric spacer.

公开(公告)号：US20230290841A1

公开(公告)日：2023-09-14

申请号：US17693141

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tsuan-Chung CHANG ,  Charles H. WALLACE ,  Tahir GHANI ,  Desalegne B. TEWELDEBRHAN

IPC: H01L29/417

CPC classification number: H01L29/41775

Abstract: Spacer self-aligned via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A corresponding one of a plurality of dielectric spacers is between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures. The plurality of dielectric spacers protrudes above the plurality of gate structures and above the plurality of conductive trench contact structures. A conductive structure is in direct contact with one of the plurality of gate structures or with one of the plurality of conductive trench contact structures. The conductive structure has a flat edge along a direction across the one of the plurality of gate structures or the one of the plurality of conductive trench contact structures.

公开(公告)号：US20230232605A1

公开(公告)日：2023-07-20

申请号：US18124936

申请日：2023-03-22

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Byron HO ,  Curtis W. WARD ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H10B10/00 ,  H01L29/66 ,  H01L27/092 ,  H01L27/06

CPC classification number: H10B10/15 ,  H10B10/125 ,  H01L29/66545 ,  H01L27/0924 ,  H01L27/0688

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

公开(公告)号：US20230200043A1

公开(公告)日：2023-06-22

申请号：US18109780

申请日：2023-02-14

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Van H. LE ,  Chieh-Jen KU ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI ,  Gregory GEORGE ,  Akash GARG ,  Julie ROLLINS ,  Allen B. GARDINER ,  Shem OGADHOH ,  Juan G. ALZATE VINASCO ,  Umut ARSLAN ,  Fatih HAMZAOGLU ,  Nikhil MEHTA ,  Yu-Wen HUANG ,  Shu ZHOU

IPC: H10B12/00

CPC classification number: H10B12/03 ,  H10B12/05 ,  H10B12/30

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

公开(公告)号：US20230187494A1

公开(公告)日：2023-06-15

申请号：US17547992

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Sukru YEMENICIOGLU ,  Tahir GHANI ,  Andy Chih-Hung WEI ,  Leonard P. GULER ,  Charles H. WALLACE ,  Mohit K. HARAN

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L29/78696 ,  H01L29/78618 ,  H01L29/42392

Abstract: A structure includes a first vertical stack of horizontal nanowires having a first width. A second vertical stack of horizontal nanowires is spaced apart from and parallel with the first vertical stack of horizontal nanowires and has the first width. A first gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, a second gate structure portion over the second vertical stack of horizontal nanowires, and a gate cut between the first gate structure portion and the second gate structure portion. A third vertical stack of horizontal nanowires has a second width greater than the first width. A fourth vertical stack of horizontal nanowires is spaced apart from and parallel with the third vertical stack of horizontal nanowires and has the second width. A second gate structure is continuous over the third vertical stack of horizontal nanowires and over the fourth vertical stack of horizontal nanowires.

公开(公告)号：US20230163215A1

公开(公告)日：2023-05-25

申请号：US18094285

申请日：2023-01-06

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Stephen SNYDER ,  Biswajeet GUHA ,  William HSU ,  Urusa ALAAN ,  Tahir GHANI ,  Michael K. HARPER ,  Vivek THIRTHA ,  Shu ZHOU ,  Nitesh KUMAR

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/165 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L29/7856 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/165 ,  H01L21/02293 ,  H01L29/0649 ,  H01L29/0847 ,  H01L21/022 ,  H01L29/1091 ,  H01L29/78696 ,  H01L29/7851

Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

公开(公告)号：US20230101725A1

公开(公告)日：2023-03-30

申请号：US17485167

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Debaleena NANDI ,  Mauro J. KOBRINSKY ,  Gilbert DEWEY ,  Chi-hing CHOI ,  Harold W. Kennel ,  Brian J. KRIST ,  Ashkar ALIYARUKUNJU ,  Cory BOMBERGER ,  Rushabh SHAH ,  Rishabh MEHANDRU ,  Stephen M. CEA ,  Chanaka MUNASINGHE ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786

Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprises silicon, and germanium that at least partially covers the epitaxial source or drain structures. A conductive contact comprising titanium silicide is on the epitaxial source or drain structures.