公开(公告)号：US07122488B2

公开(公告)日：2006-10-17

申请号：US10812591

申请日：2004-03-29

Applicant: Pooran Chandra Joshi ,  Apostolos T. Voutsas ,  John W. Hartzell

Inventor： Pooran Chandra Joshi ,  Apostolos T. Voutsas ,  John W. Hartzell

IPC: H01L21/469 ,  H01L21/31

CPC classification number: H01L21/049 ,  C23C16/0272 ,  C23C16/402 ,  C23C16/509 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02274 ,  H01L21/045 ,  H01L21/31612

Abstract: Methods are provided for forming silicon dioxide (SiO2) on a silicon carbide (SiC) substrate. The method comprises: providing a SiC substrate; supplying an atmosphere including oxygen; performing a high-density (HD) plasma-based process; and, forming a SiO2 layer overlying the SiC substrate. Typically, performing the HD plasma-based process includes connecting a top electrode to an inductively coupled HD plasma source. In one aspect, SiO2 is grown on the SiC substrate. Then, an HD plasma oxidation process is performed that creates a reactive oxygen species and breaks the Si—C bonds in the SiC substrate, to form free Si and C atoms in the SiC substrate. The free Si atoms in the SiC substrate are bonded to the HD plasma-generated reactive oxygen species, and the SiO2 layer is grown.

Abstract translation: 提供了在碳化硅（SiC）衬底上形成二氧化硅（SiO 2）的方法。 该方法包括：提供SiC衬底; 提供包含氧气的气氛; 执行高密度（HD）等离子体工艺; 并且形成覆盖在SiC衬底上的SiO 2层。 通常，执行基于HD等离子体的工艺包括将顶部电极连接到电感耦合的HD等离子体源。 在一个方面，在SiC衬底上生长SiO 2。 然后，进行HD等离子体氧化处理，其产生活性氧物质并破坏SiC衬底中的Si-C键，以在SiC衬底中形成游离的Si和C原子。 SiC衬底中的自由Si原子与HD等离子体产生的活性氧结合，并且生长SiO 2层。

公开(公告)号：US06278876B1

公开(公告)日：2001-08-21

申请号：US09115098

申请日：1998-07-13

Applicant: Chandra Joshi ,  Anthony Noerpel ,  Neeraj Tewari ,  Gerard Stelzer ,  David Roos ,  Chi-Jiun Su

Inventor： Chandra Joshi ,  Anthony Noerpel ,  Neeraj Tewari ,  Gerard Stelzer ,  David Roos ,  Chi-Jiun Su

IPC: H04Q720

CPC classification number: H04B7/2125 ,  H04B7/18517 ,  H04B7/18539 ,  H04B7/18543 ,  H04B7/18558 ,  H04B7/18567 ,  H04B7/18571 ,  H04B7/1858 ,  H04B7/18582 ,  H04B7/19 ,  H04B7/2041 ,  H04W28/14 ,  H04W52/0203 ,  H04W52/0216 ,  H04W72/0413 ,  H04W72/042 ,  H04W74/00 ,  H04W76/10 ,  H04W76/25 ,  H04W80/00 ,  H04W84/06 ,  Y02D70/1222 ,  Y02D70/164 ,  Y02D70/20 ,  Y02D70/446

Abstract: A system and method for implementing single hop space segment terminal to terminal connections. The system includes a satellite-based radio frequency (RF) communication link for conveying multiple communication channels over the space segment via one or more spot beams. A terrestrial supervisory transceiver such as a gateway station is provided in communication with the satellite-based communication link. Mobile hand-held terminals (HHTs), herein first and second access terminals, may be located within one or more of the spot beams to communicate with one another via a single hop connection through a satellite of the system. A switch is provided for communication switching with the satellite of the system for the multiple communication channels to couple the first access terminal and the second access terminal over the space segment via one or more of the spot beams. The terrestrial supervisory transceiver or gateway is provided in communication with the satellite switch via the satellite-based communication link for implementing the single hop space segment terminal to terminal connection.

Abstract translation: 一种实现单跳空间段终端到终端连接的系统和方法。 该系统包括用于经由一个或多个点波束在空间段上传送多个通信信道的基于卫星的射频（RF）通信链路。 提供与卫星通信链路通信的诸如网关站的地面监控收发器。 本文中的第一和第二接入终端中的移动手持终端（HHT）可以位于一个或多个点波束内，以经由通过系统的卫星的单跳连接来彼此通信。 提供了用于与用于多个通信信道的系统的卫星进行通信切换的开关，以通过一个或多个点波束将空间段上的第一接入终端和第二接入终端耦合。 提供地面监控收发信机或网关，通过基于卫星的通信链路与卫星交换机通信，实现单跳空间段终端到终端连接。

公开(公告)号：US5954815A

公开(公告)日：1999-09-21

申请号：US781851

申请日：1997-01-10

Applicant: Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

Inventor： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

IPC: G06F9/32 ,  G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3844

Abstract: A computing system that contains an apparatus comprising an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address. A counter stores an address value used for addressing the instruction memory, and an incrementing circuit increments the address value in the counter for sequentially addressing the lines in the instruction memory during normal sequential operation. A counter loading circuit loads the target address into the counter when the branch prediction entry predicts the branch designated by the branch instruction stored in the instruction memory will be taken when the branch instruction is executed, causing the line containing the target instruction to be fetched and entered into the pipeline immediately after the line containing the branch instruction. An invalidate circuit invalidates any instructions following the branch instruction in the line containing the branch instruction and prior to the target instruction in the line containing the target instruction.

Abstract translation: 一种计算系统，包括包括存储多条指令的多行的指令存储器和存储多个分支预测条目的分支存储器的装置，每个分支预测条目包含用于预测由a 当执行分支指令时，将采用存储在指令存储器中的分支指令。 每个分支预测条目包括用于指示包含要执行的目标指令的行的目标地址的分支目标字段，如果分支被采用，则指示目标指令位于由分支目标地址指示的行内的目的地字段， 以及指示分支指令在与目标地址对应的行内位于何处的源字段。 计数器存储用于寻址指令存储器的地址值，并且递增电路递增计数器中的地址值，以便在正常顺序操作期间顺序寻址指令存储器中的行。 当分支预测条目预测在执行分支指令时，将采用存储在指令存储器中的分支指令指定的分支，计数器加载电路将目标地址加载到计数器中，导致包含目标指令的行被取出， 在包含分支指令的行后立即进入管道。 无效电路使包含分支指令的行中的分支指令之后的指令和包含目标指令的行中的目标指令之前的任何指令无效。

公开(公告)号：US20150113221A1

公开(公告)日：2015-04-23

申请号：US13997426

申请日：2013-03-15

Applicant: Herbert Hum ,  Chandra Joshi ,  Rahul Pal ,  Luke Chang

Inventor： Herbert Hum ,  Chandra Joshi ,  Rahul Pal ,  Luke Chang

IPC: G06F12/08

CPC classification number: G06F12/0871 ,  G06F12/0875 ,  G06F2212/225 ,  G06F2212/452 ,  Y02D10/13

Abstract: A first processor receives a write request from an input/output (I/O) device connected to the first processor. The first processor determines whether the write request satisfies an allocating write criterion. Responsive to determining that the write request satisfies the allocating write criterion, the first processor writes data associated with the write request to a cache of the first processor.

Abstract translation: 第一处理器从连接到第一处理器的输入/输出（I / O）设备接收写请求。 第一处理器确定写入请求是否满足分配写入标准。 响应于确定写请求满足分配写标准，第一处理器将与写请求相关联的数据写入第一处理器的高速缓存。

公开(公告)号：US08958254B2

公开(公告)日：2015-02-17

申请号：US13402429

申请日：2012-02-22

Applicant: Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Lakshmikantha Vakwadi Holla

Inventor： Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Lakshmikantha Vakwadi Holla

IPC: G11C7/00

CPC classification number: G11C11/419 ,  G11C8/18

Abstract: An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.

Abstract translation: 8T存储器单元接收时钟信号并读取和写入地址信号。 读地址锁存/时钟电路接收时钟信号和读地址信号，并在第一时钟周期状态期间启动读操作。 写地址触发器/时钟电路在第二时钟周期状态期间接收时钟信号和写入地址信号并发起写入操作。 逆变器接收并反相时钟信号，并将反相时钟信号施加到写入地址触发器/时钟电路。 读地址锁存/时钟电路在第二时钟周期状态期间启动读字线预充电操作和在第一时钟周期状态期间的写字线预充电操作。 写地址触发器/时钟电路还可以包括松开的自拍以结束写周期是时钟信号持续超过预定时间。

公开(公告)号：US08349745B2

公开(公告)日：2013-01-08

申请号：US12267698

申请日：2008-11-10

Applicant: Pooran Chandra Joshi ,  Hao Zhang ,  Jiandong Huang ,  Apostolos T. Voutsas

Inventor： Pooran Chandra Joshi ,  Hao Zhang ,  Jiandong Huang ,  Apostolos T. Voutsas

IPC: H01L21/31

CPC classification number: C23C16/30 ,  C23C16/5096 ,  C23C16/56

Abstract: A method is provided for fabricating a semiconductor nanoparticle embedded Si insulating film for short wavelength luminescence applications. The method provides a bottom electrode, and deposits a semiconductor nanoparticle embedded Si insulating film, including the element of N, O, or C, overlying the bottom electrode. After annealing, a semiconductor nanoparticle embedded Si insulating film has a peak photoluminescence (PL) at a wavelength in the range of 475 to 750 nanometers.

Abstract translation: 提供一种用于制造用于短波长发光应用的半导体纳米颗粒嵌入式Si绝缘膜的方法。 该方法提供底部电极，并沉积包含覆盖底部电极的N，O或C元素的半导体纳米颗粒嵌入的Si绝缘膜。 在退火之后，半导体纳米颗粒嵌入的Si绝缘膜在475至750纳米的波长范围内具有峰值光致发光（PL）。

公开(公告)号：US08236244B2

公开(公告)日：2012-08-07

申请号：US11827173

申请日：2007-07-10

Applicant: John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele

Inventor： John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele

IPC: G01J3/00

CPC classification number: B01J19/0046 ,  B01J2219/0061 ,  B01J2219/00614 ,  B01J2219/00659 ,  B01J2219/00675 ,  B01J2219/00677 ,  B01J2219/00689 ,  B01J2219/00711 ,  B01J2219/00722 ,  B82Y30/00 ,  C12Q1/6837 ,  C40B50/14 ,  C40B60/08 ,  G01N21/645 ,  G01N2021/6482 ,  Y10T29/49 ,  Y10T436/143333

Abstract: A digitally-addressable, pixelated, DNA fluid-assay, active-matrix micro-structure formed, utilizing low-temperature TFT and Si technology, on a substrate preferably made of glass or plastic, and including at least one pixel which is defined by (a) an addressable pixel site, (b) a sensor home structure disposed within that site for receiving and hosting a functionalized assay site possessing a DNA oligonucleotide probe, and (c) an addressable, pixel-site-specific, energy-field-producing functionalizer (preferably optical) operable to functionalize such a probe on the assay site. Each pixel may also include a pixel-integrated optical detector. Further disclosed are related methodology facets involving (1) the making of such a micro-structure (a) in a precursor form (without a functionalized probe), and thereafter (b) in a finalized/functionalized form (with such a probe), and (2) the ultimate use of a completed micro-structure in the performance of a DNA assay.

Abstract translation: 在优选由玻璃或塑料制成的衬底上，利用低温TFT和Si技术形成的可数字寻址，像素化，DNA流体测定，有源矩阵微结构，并且包括至少一个由（ a）可寻址像素位点，（b）设置在所述位置内的用于接收和承载具有DNA寡核苷酸探针的官能化测定位点的传感器家庭结构，和（c）可寻址的像素位点特异性能量场产生 功能化剂（优选光学）可操作以在测定位点官能化这种探针。 每个像素还可以包括像素集成的光学检测器。 进一步公开的是相关的方法学方面，其涉及（1）以前体形式（无官能化探针）制备这种微结构（a），此后（b）以最终/功能化形式（具有这种探针）， 和（2）在DNA测定的表现中最终使用完整的微结构。

公开(公告)号：US08007332B2

公开(公告)日：2011-08-30

申请号：US12187605

申请日：2008-08-07

Applicant: Pooran Chandra Joshi ,  Jiandong Huang ,  Apostolos T. Voutsas

Inventor： Pooran Chandra Joshi ,  Jiandong Huang ,  Apostolos T. Voutsas

IPC: H01J9/24

CPC classification number: C23C16/30 ,  C23C16/24 ,  C23C16/401 ,  C23C16/402 ,  C23C16/505 ,  C23C16/56 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/0262 ,  H01L21/31608 ,  H01L33/18

Abstract: A method is provided for fabricating a semiconductor nanoparticle embedded Si insulating film for electroluminescence (EL) applications. The method provides a bottom electrode, and deposits a semiconductor nanoparticle embedded Si insulating film, including an element selected from a group consisting of N and C, overlying the bottom electrode. After annealing, a semiconductor nanoparticle embedded Si insulating film is formed having an extinction coefficient (k) in a range of 0.01-1.0, as measured at about 632 nanometers (nm), and a current density (J) of greater than 1 Ampere per square centimeter (A/cm2) at an applied electric field lower than 3 MV/cm. In another aspect, the annealed semiconductor nanoparticle embedded Si insulating film has an index of refraction (n) in a range of 1.8-3.0, as measured at 632 nm, with a current density of greater than 1 A/cm2 at an applied electric field lower than 3 MV/cm.

Abstract translation: 提供了一种用于制造用于电致发光（EL）应用的半导体纳米颗粒嵌入的Si绝缘膜的方法。 该方法提供底部电极，并且沉积半导体纳米颗粒嵌入的Si绝缘膜，其包括选自N和C组成的组的元素，覆盖在底部电极上。 在退火之后，形成半导体纳米颗粒嵌入的Si绝缘膜，其消光系数（k）在0.01〜1.0的范围内，在大约632纳米（nm）测量，电流密度（J）大于1安培 在施加的电场低于3MV / cm下的平方厘米（A / cm 2）。 在另一方面，被退火的半导体纳米颗粒嵌入的Si绝缘膜的折射率（n）在632nm处测量的范围为1.8-3.0，在施加的电场下的电流密度大于1A / cm 2 低于3 MV / cm。

公开(公告)号：US07916986B2

公开(公告)日：2011-03-29

申请号：US12112767

申请日：2008-04-30

Applicant: Hao Zhang ,  Pooran Chandra Joshi ,  Apostolos T. Voutsas

Inventor： Hao Zhang ,  Pooran Chandra Joshi ,  Apostolos T. Voutsas

IPC: G02B6/26 ,  B05D5/06 ,  C23C14/48 ,  C23C14/16 ,  C23F1/00 ,  H01L21/00

CPC classification number: C23C16/30 ,  C23C16/56 ,  H01L21/02156 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/02362 ,  H01L21/31608

Abstract: An erbium (Er)-doped silicon (Si) nanocrystalline embedded silicon oxide (SiOx) waveguide and associated fabrication method are presented. The method provides a bottom layer, and forms an Er-doped Si nanocrystalline embedded SiOx film waveguide overlying the bottom layer, having a minimum optical attenuation at about 1540 nanometers (nm). Then, a top layer is formed overlying the Er-doped SiOx film. The Er-doped SiOx film is formed by depositing a silicon rich silicon oxide (SRSO) film using a high density plasma chemical vapor deposition (HDPCVD) process and annealing the SRSO film. After implanting Er+ ions, the Er-doped SiOx film is annealed again. The Er-doped Si nanocrystalline SiOx film includes has a first refractive index (n) in the range of 1.46 to 2.30. The top and bottom layers have a second refractive index, less than the first refractive index.

Abstract translation: 提出了一种铒（Er）掺杂的硅（Si）纳米晶体嵌入式氧化硅（SiOx）波导及其制造方法。 该方法提供底层，并且形成覆盖底层的掺​​铒Si纳米晶体的包含SiOx的薄膜波导，在约1540纳米（nm）处具有最小的光衰减。 然后，形成覆盖Er掺杂的SiOx膜的顶层。 通过使用高密度等离子体化学气相沉积（HDPCVD）方法沉积富硅氧化物（SRSO）膜并退火SRSO膜来形成Er掺杂的SiOx膜。 在注入Er +离子后，再次对Er掺杂的SiOx膜进行退火。 掺铒Si纳米晶SiOx膜的第一折射率（n）在1.46〜2.30的范围内。 顶层和底层具有小于第一折射率的第二折射率。

公开(公告)号：US07786021B2

公开(公告)日：2010-08-31

申请号：US11264979

申请日：2005-11-02

Applicant: Pooran Chandra Joshi ,  Apostolos T. Voutsas

Inventor： Pooran Chandra Joshi ,  Apostolos T. Voutsas

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L29/4908 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/28008 ,  H01L21/31612 ,  H01L29/6675 ,  H01L29/78642

Abstract: A thin-film transistor (TFT) with a multilayer gate insulator is provided, along with a method for forming the same. The method comprises: forming a channel, first source/drain (S/D) region, and a second S/D region in a Silicon (Si) active layer; using a high-density plasma (HDP) source, growing a first layer of Silicon oxide (SiOx) from the Si active layer, to a first thickness, where x is less than, or equal to 2; depositing a second layer of SiOx having a second thickness, greater than the first thickness, overlying the first layer of SiOx; using the HDP source, additionally oxidizing the second layer of SiOx, wherein the first and second SiOx layers form a gate insulator; and, forming a gate electrode adjacent the gate insulator. In one aspect, the second Si oxide layer is deposited using a plasma-enhanced chemical vapor deposition (PECVD) process with tetraethylorthosilicate (TEOS) precursors.

Abstract translation: 提供具有多层栅极绝缘体的薄膜晶体管（TFT）及其形成方法。 该方法包括：在硅（Si）有源层中形成沟道，第一源/漏（S / D）区和第二S / D区; 使用高密度等离子体（HDP）源，从Si活性层生长第一层氧化硅（SiO x）至第一厚度，其中x小于或等于2; 在SiOx的第一层上沉积具有大于第一厚度的第二厚度的第二SiO x层; 使用HDP源，另外氧化SiO x的第二层，其中第一和第二SiO x层形成栅极绝缘体; 并且形成与栅极绝缘体相邻的栅电极。 在一个方面，使用等离子体增强化学气相沉积（PECVD）法与原硅酸四乙酯（TEOS）前体沉积第二Si氧化物层。