公开(公告)号：US20050067634A1

公开(公告)日：2005-03-31

申请号：US10950477

申请日：2004-09-28

Applicant: Cay-Uwe Pinnow ,  Martin Gutsche ,  Harald Seidl ,  Thomas Happ

Inventor： Cay-Uwe Pinnow ,  Martin Gutsche ,  Harald Seidl ,  Thomas Happ

IPC: G03G15/02 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L21/28282 ,  H01L29/42332 ,  H01L29/7881 ,  Y10S438/954

Abstract: A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.

Abstract translation: 非易失性集成半导体存储器具有具有隧道势垒层和电荷存储电平的层的排列。 电荷储存电平具有在空间固定位置中分散存储在电荷载体中的电介质材料。 隧道势垒层具有高能电荷载流子穿过的材料。 电荷存储水平的至少一个界面表面具有比远离电荷存储水平的隧道势垒层的界面更大的微观粗糙度。 电荷存储水平在第一区域中具有比在第二区域中更大的层厚度。 这在横向方向产生正电荷载体和负电荷载体的相对相同的分布和定位。 因此，分散到电荷存储电平的电荷载体完全复合，从而降低了在非易失性存储器的长期操作期间不可预见的数据丢失的风险。

公开(公告)号：US06853023B2

公开(公告)日：2005-02-08

申请号：US10356780

申请日：2003-01-31

Applicant: Bernd Goebel ,  Jörn Lützen ,  Martin Popp ,  Harald Seidl

Inventor： Bernd Goebel ,  Jörn Lützen ,  Martin Popp ,  Harald Seidl

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864

Abstract: A semiconductor memory cell configuration includes dynamic memory cells respectively having a trench capacitor and a vertical selection transistor, the memory cells being disposed in matrix form, the trench capacitors and the associated vertical selection transistors following one another in each case in the form of rows and/or columns.

Abstract translation: 半导体存储单元配置包括分别具有沟槽电容器和垂直选择晶体管的动态存储器单元，存储单元以矩阵形式布置，沟槽电容器和相关联的垂直选择晶体管在每种情况下彼此以行的形式相互依次， /或列。

公开(公告)号：US06835417B2

公开(公告)日：2004-12-28

申请号：US10375529

申请日：2003-02-27

Applicant: Annette Saenger ,  Bernhard Sell ,  Harald Seidl ,  Thomas Hecht ,  Martin Gutsche

Inventor： Annette Saenger ,  Bernhard Sell ,  Harald Seidl ,  Thomas Hecht ,  Martin Gutsche

IPC: C23C1600

CPC classification number: C23C16/45527 ,  C23C16/34 ,  C23C16/40 ,  C23C16/42 ,  C23C16/45544 ,  C23C16/46 ,  C23C16/481

Abstract: The ALD process chamber has heating radiation sources and the process sequence includes rapid temperature changes on a substrate surface of a substrate arranged in the ALD process chamber. The temperature changes are controlled and the ALD and CVD processes are optimized by in situ temperature steps, for example in order to produce nanolaminates.

Abstract translation: ALD处理室具有加热辐射源，并且工艺顺序包括在布置在ALD处理室中的衬底的衬底表面上的快速温度变化。 控制温度变化，并通过原位温度步骤优化ALD和CVD工艺，例如为了生产纳米级氨基酸。

公开(公告)号：US07978504B2

公开(公告)日：2011-07-12

申请号：US12131938

申请日：2008-06-03

Applicant: Ronald Kakoschke ,  Harald Seidl

Inventor： Ronald Kakoschke ,  Harald Seidl

IPC: G11C11/00

CPC classification number: H01L21/28282 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4966

Abstract: One or more embodiments relate to a memory device, comprising: a substrate; a charge storage layer disposed over the substrate; and a control gate disposed over the charge storage layer, wherein the charge storage layer or the control gate layer comprises a carbon allotrope.

Abstract translation: 一个或多个实施例涉及一种存储器件，包括：衬底; 设置在所述基板上的电荷存储层; 以及设置在所述电荷存储层上的控制栅极，其中所述电荷存储层或所述控制栅极层包含碳同素异形体。

公开(公告)号：US20090294832A1

公开(公告)日：2009-12-03

申请号：US12131938

申请日：2008-06-03

Applicant: Ronald KAKOSCHKE ,  Harald SEIDL

Inventor： Ronald KAKOSCHKE ,  Harald SEIDL

IPC: H01L29/792 ,  H01L29/788

CPC classification number: H01L21/28282 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4966

Abstract: One or more embodiments relate to a memory device, comprising: a substrate; a charge storage layer disposed over the substrate; and a control gate disposed over the charge storage layer, wherein the charge storage layer or the control gate layer comprises a carbon allotrope.

Abstract translation: 一个或多个实施例涉及一种存储器件，包括：衬底; 设置在所述基板上的电荷存储层; 以及设置在所述电荷存储层上的控制栅极，其中所述电荷存储层或所述控制栅极层包含碳同素异形体。

公开(公告)号：US20090014889A1

公开(公告)日：2009-01-15

申请号：US11416712

申请日：2006-05-03

Applicant: Hans-Joachim Barth ,  Harald Seidl

Inventor： Hans-Joachim Barth ,  Harald Seidl

IPC: H01L23/52 ,  H01L21/00 ,  B32B37/00

CPC classification number: H01L24/95 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/3185 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2924/14 ,  Y10T156/12 ,  H01L2924/00

Abstract: The present disclosures relates to a method for producing ultrathin chip stacks and chip stacks. Generally, a plurality of first semiconductor chips is formed in a wafer. A second semiconductor chip is applied to each of the plurality of first semiconductor chips via a connection layer and a stabilization layer is applied to fill in the interspace between each of the second semiconductor chips. The wafer, semiconductor chip, and stabilization layer are thinned and the wafer is sawed to produce a plurality of singulated chip stacks.

Abstract translation: 本发明涉及一种用于生产超薄芯片堆叠和芯片堆叠的方法。 通常，在晶片中形成多个第一半导体芯片。 经由连接层将第二半导体芯片施加到多个第一半导体芯片中的每一个，并且施加稳定层以填充每个第二半导体芯片之间的间隙。 将晶片，半导体芯片和稳定层减薄，并锯切晶片以产生多个单片芯片堆叠。

公开(公告)号：US07312115B2

公开(公告)日：2007-12-25

申请号：US11127505

申请日：2005-05-12

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L21/8242

CPC classification number: H01L28/92 ,  H01L27/0805 ,  H01L27/1087 ,  H01L28/91 ,  H01L29/66181 ,  H01L29/945

Abstract: The present invention provides a fabrication method for a semiconductor structure having integrated capacitors and a corresponding semiconductor structure. The fabrication method has the following steps of: providing a semiconductor substrate (1; 1′, 60, 1″) having a front side (VS) and a rear side (RS); providing trenches (5) in the semiconductor substrate (1; 1′, 60, 1″) proceeding from the front side (VS) of the semiconductor substrate (1; 1′, 60, 1″); providing a respective inner capacitor electrode (6) in the trenches (5); uncovering the inner capacitor electrodes (6) proceeding from the rear side (RS) of the semiconductor substrate (1; 1′, 60, 1″); providing a capacitor dielectric (40) on the uncovered inner capacitor electrodes (6); and providing outer capacitor electrodes (50) on the capacitor dielectric (40) on the inner capacitor electrodes (6).

Abstract translation: 本发明提供一种具有集成电容器和相应的半导体结构的半导体结构的制造方法。 该制造方法具有以下步骤：提供具有前侧（VS）和后侧（RS）的半导体衬底（1; 1'，60“1”）; 在半导体衬底（1; 1'，60“1”）的前侧（VS）上提供在半导体衬底（1; 1'，60“1”）中的沟槽（5） 在沟槽（5）中提供相应的内部电容器电极（6）; 露出从半导体衬底（1; 1'，60,1“）的后侧（RS）延伸的内部电容器电极（6）; 在未覆盖的内部电容器电极（6）上提供电容器电介质（40）; 以及在内部电容器电极（6）上的电容器电介质（40）上提供外部电容器电极（50）。

公开(公告)号：US20070145346A1

公开(公告)日：2007-06-28

申请号：US11390560

申请日：2006-03-28

Applicant: Harald Seidl

Inventor： Harald Seidl

IPC: H01L29/04

CPC classification number: H01L45/06 ,  G11C2213/52 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1683

Abstract: The present disclosure relates to a connection electrode for phase change materials, to an associated phase change memory element and to an associated production process, wherein a plurality of separate insulation regions are formed in an electrode material at least at a connection surface. This reduces the overall size of the contact surface, with the result that even with high integration densities, the necessary Joule heating, and therefore programming, at very low currents can be realized.

Abstract translation: 本公开内容涉及用于相变材料的连接电极，相关联的相变存储元件和相关联的制造工艺，其中在电极材料中至少在连接表面处形成多个单独的绝缘区域。 这就降低了接触表面的整体尺寸，从而即使在高集成密度的情况下，也可以实现在非常低的电流下所需的焦耳加热，因此编程。

公开(公告)号：US20070134871A1

公开(公告)日：2007-06-14

申请号：US11702162

申请日：2007-02-05

Applicant: Dietmar Temmler ,  Martin Gutsche ,  Martin Popp ,  Harald Seidl

Inventor： Dietmar Temmler ,  Martin Gutsche ,  Martin Popp ,  Harald Seidl

IPC: H01L21/8242

CPC classification number: H01L27/10867 ,  H01L27/10832 ,  H01L27/10864

Abstract: Memory cells having trench capacitors, the trench capacitor being at least partially filled with a material which could not withstand high-temperature processes used during the fabrication of a memory chip without impairment of its electrical parameters. What is essential to the invention is that the material of the trench capacitor is introduced into the trench after the high-temperature processes. The method according to the invention makes it possible to use dielectric layers having large dielectric constants and electrode layers made of metallic material. The electrical properties of the trench capacitor are thus improved in comparison with known trench capacitors.

Abstract translation: 具有沟槽电容器的存储单元，沟槽电容器至少部分地填充有不能承受在制造存储器芯片期间使用的高温处理而不损害其电参数的材料。 本发明的重要内容是在高温处理之后将沟槽电容器的材料引入沟槽。 根据本发明的方法使得可以使用具有大介电常数的电介质层和由金属材料制成的电极层。 与已知的沟槽电容器相比，沟槽电容器的电性能得到改善。

公开(公告)号：US07157371B2

公开(公告)日：2007-01-02

申请号：US10653599

申请日：2003-09-02

Applicant: Thomas Hecht ,  Uwe Schroeder ,  Harald Seidl ,  Martin Gutsche ,  Stefan Jakschik ,  Stephan Kudelka ,  Albert Birner

Inventor： Thomas Hecht ,  Uwe Schroeder ,  Harald Seidl ,  Martin Gutsche ,  Stefan Jakschik ,  Stephan Kudelka ,  Albert Birner

IPC: H01L21/44

CPC classification number: H01L27/11502 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/28061 ,  H01L21/31138 ,  H01L21/31604 ,  H01L21/3162 ,  H01L21/76802 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L27/11507 ,  H01L28/57 ,  H01L29/0895 ,  H01L29/4941

Abstract: A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing semiconductor devices by sequential gas phase deposition or molecular beam epitaxy in molecular individual layers on differently structured base substrates. The method allows, inter alias, effective conductive diffusion barriers to be formed from a dielectric material, an optimization of the layer thickness of the barrier layer, an increase in the temperature budget for subsequent process steps, and a reduction in the effort for removing the temporary barrier layers.

Abstract translation: 由金属氧化物构成的电介质阻挡层通过在不同结构的基底衬底上的分子单层中的顺序气相沉积或分子束外延处理半导体器件的过程中以小于20纳米的厚度施加。 该方法允许间隔地从电介质材料形成有效的导电扩散阻挡层，优化阻挡层的层厚度，随后的工艺步骤的温度预算的增加以及用于去除 临时阻隔层。