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    Electrostatic discharge (ESD) protection circuit
    21.
    发明授权
    Electrostatic discharge (ESD) protection circuit 有权
    静电放电（ESD）保护电路

    公开(公告)号：US08390024B2

    公开(公告)日：2013-03-05

    申请号：US12757612

    申请日：2010-04-09

    Applicant: Liping Ren ,  Hsiao-Chin Tuan ,  Dah-Chuen Ho

    Inventor： Liping Ren ,  Hsiao-Chin Tuan ,  Dah-Chuen Ho

    IPC: H01L27/06

    CPC classification number: H01L27/0259 ,  H01L2224/16225 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

    Abstract: An electrostatic discharge (ESD) protection circuit includes at least one bipolar transistor. At least one isolation structure is disposed in a substrate. The at least one isolation structure is configured to electrically isolate two terminals of the at least one bipolar transistor. At least one diode is electrically coupled with the at least one bipolar transistor, wherein a junction interface of the at least one diode is disposed adjacent the at least one isolation structure.

    Abstract translation: 静电放电（ESD）保护电路包括至少一个双极晶体管。 在衬底中设置至少一个隔离结构。 所述至少一个隔离结构被配置为电隔离所述至少一个双极晶体管的两个端子。 至少一个二极管与所述至少一个双极晶体管电耦合，其中所述至少一个二极管的结界面邻近所述至少一个隔离结构设置。

    Power MOSFETs and methods for forming the same
    23.
    发明授权
    Power MOSFETs and methods for forming the same 有权
    功率MOSFET及其形成方法

    公开(公告)号：US08664718B2

    公开(公告)日：2014-03-04

    申请号：US13348463

    申请日：2012-01-11

    Applicant: Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

    Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

    IPC: H01L29/66

    CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/456 ,  H01L29/66659

    Abstract: A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region. A bottom metal layer is over the field plate.

    Abstract translation: 功率MOSFET包括从半导体衬底的顶表面延伸到半导体衬底中的半导体区域，其中半导体区域是第一导电类型。 栅极电介质和栅电极设置在半导体区域上。 与第一导电类型相反的第二导电类型的漂移区域从半导体衬底的顶表面延伸到半导体衬底中。 电介质层具有在漂移区的顶表面上方并与其接触的部分。 导电场板在电介质层的上方。 源极区域和漏极区域在栅电极的相对侧上。 漏极区域与第一漂移区域接触。 底部金属层在场板上。

    Semiconductor device having multi-thickness gate dielectric
    24.
    发明授权
    Semiconductor device having multi-thickness gate dielectric 有权
    具有多层栅极电介质的半导体器件

    公开(公告)号：US08461647B2

    公开(公告)日：2013-06-11

    申请号：US12721045

    申请日：2010-03-10

    Applicant: Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao-Chin Tuan

    Inventor： Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao-Chin Tuan

    IPC: H01L29/66

    CPC classification number: H01L29/42368 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

    Abstract: A semiconductor device is provided that, in an embodiment, is in the form of a high voltage MOS (HVMOS) device. The device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. The gate structure includes a gate dielectric which has a first portion with a first thickness and a second portion with a second thickness. The second thickness is greater than the first thickness. A gate electrode is disposed on the first and second portion. In an embodiment, a drift region underlies the second portion of the gate dielectric. A method of fabricating the same is also provided.

    Abstract translation: 提供了一种半导体器件，其在一个实施例中是高压MOS（HVMOS）器件的形式。 该器件包括形成在半导体衬底上的半导体衬底和栅极结构。 栅极结构包括具有第一厚度的第一部分和具有第二厚度的第二部分的栅极电介质。 第二厚度大于第一厚度。 栅电极设置在第一和第二部分上。 在一个实施例中，漂移区域位于栅极电介质的第二部分的下方。 还提供了一种制造该方法的方法。

    Quasi-vertical structure for high voltage MOS device
    25.
    发明授权
    Quasi-vertical structure for high voltage MOS device 有权
    高电压MOS器件的准垂直结构

    公开(公告)号：US08445955B2

    公开(公告)日：2013-05-21

    申请号：US12699397

    申请日：2010-02-03

    Applicant: Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao Chin Tuan

    Inventor： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao Chin Tuan

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/7827 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7809

    Abstract: A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer.

    Abstract translation: 半导体器件提供高击穿电压和低导通电阻。 该装置包括：基板; 埋设在衬底中的n +层; 设置在掩埋的n +层上的n外延层; 设置在n外延层中的p阱; 源极n +区域，设置在p阱中并连接到一侧的源极触点; 设置在p阱和n外延层顶部的第一绝缘层; 设置在所述第一绝缘层的顶部上的栅极; 以及从掩埋n +层延伸到漏极接触的金属电极，其中金属电极通过第二绝缘层与n外延层和p阱绝缘。

    Polysilicon undercut process for stack DRAM
    29.
    发明授权
    Polysilicon undercut process for stack DRAM 失效
    堆叠DRAM的多晶硅底切工艺

    公开(公告)号：US5374577A

    公开(公告)日：1994-12-20

    申请号：US993625

    申请日：1992-12-21

    Applicant: Hsiao-Chin Tuan

    Inventor： Hsiao-Chin Tuan

    IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC classification number: H01L27/10852 ,  H01L28/87

    Abstract: A method for fabricating DRAM capacitors is described. Field effect devices are foraged in the silicon substrate. A first oxide layer is formed over the device and field oxide areas. The capacitors are formed by first depositing a heavily doped silicon layer over the device and field oxide areas. Then forming openings to the desired source/drain structures by etching through the silicon layer, and first oxide layers, wherein the opening extends over a portion of the gate electrode polysilicon layer of the gate structure and the field oxide areas. An undoped polysilicon layer is deposited over the openings to the source/drain structures. Patterning anisotropically the silicon and molysilicon layers so as to have their remaining portions over the planned capacitor areas, and wherein a portion of the heavily doped silicon layer remains over both the portion of the polysilicon gate electrode of the gate structure and the field oxide areas. Then completely removing by selective etching the portion of heavily doped silicon layer using phosphoric acid at a temperature greater than 140.degree. C. to create an undercut of the undoped polysilicon layer over both the portion of the polysilicon gate electrode of the gate structure and the field oxide areas and to construct the bottom storage node electrode of the desired capacitor. The capacitor is then completed.

    Abstract translation: 描述了制造DRAM电容器的方法。 场效应器件在硅衬底中被使用。 在器件和场氧化物区域上形成第一氧化物层。 通过首先在器件和场氧化物区域上沉积重掺杂的硅层来形成电容器。 然后通过蚀刻穿过硅层和第一氧化物层形成到期望的源极/漏极结构的开口，其中开口延伸在栅极结构的栅电极多晶硅层的一部分和场氧化物区域上。 未掺杂的多晶硅层沉积在开口上到源/漏结构。 各向异性地形成硅和钼硅层，使其剩余部分在规划的电容器区域上，并且其中重掺杂硅层的一部分保留在栅极结构的多晶硅栅电极的部分和场氧化物区域之上。 然后通过在大于140℃的温度下使用磷酸选择性蚀刻重掺杂硅层的部分来完全去除以在栅极结构的多晶硅栅电极的两个部分上形成未掺杂的多晶硅层的底切， 并构成所需电容器的底部存储节点电极。 然后电容器完成。

    Method for producing a roughened surface capacitor
    30.
    发明授权
    Method for producing a roughened surface capacitor 失效
    粗糙表面电容器的制造方法

    公开(公告)号：US5266514A

    公开(公告)日：1993-11-30

    申请号：US994501

    申请日：1992-12-21

    Applicant: Hsiao-Chin Tuan ,  Hsiang-Ming J. Chou

    Inventor： Hsiao-Chin Tuan ,  Hsiang-Ming J. Chou

    IPC: H01L21/02 ,  H01L21/306 ,  H01L21/8242 ,  H01L21/70 ,  H01L27/00

    CPC classification number: H01L27/10852 ,  H01L21/30604 ,  H01L28/84 ,  Y10S438/964

    Abstract: A new method to produce a microminiturized capacitor having a roughened surface electrode is achieved. The method involves depositing a first polycrystalline or amorphous silicon layer over a suitable insulating base. The silicon layer is either in situ heavily, uniformly doped or deposited undoped and thereafter heavily doped by ion implantation followed by heating. The structure is annealed at above about 875.degree. C. to render any amorphous silicon polycrystalline and to adjust the crystal grain size of the layer. The polysilicon surface is no subjected to a solution of phosphoric acid at a temperature of above about 140.degree. C. to partially etch the surface and cause the uniformly roughened surface. A capacitor dielectric layer is deposited thereover. The capacitor structure is completed by depositing a second thin polycrystalline silicon layer over the capacitor dielectric layer.

    Abstract translation: 实现了一种生产具有粗糙表面电极的微量化电容器的新方法。 该方法包括在合适的绝缘基底上沉积第一多晶或非晶硅层。 硅层原位沉积，均匀掺杂或沉积未掺杂，然后通过离子注入重复掺杂，然后加热。 该结构在高于约875℃下退火以形成任何非晶硅多晶并调节该层的晶粒尺寸。 多晶硅表面在高于约140℃的温度下不经受磷酸溶液，以部分蚀刻表面并引起均匀的粗糙化表面。 在其上沉积电容器介电层。 通过在电容器介电层上沉积第二薄多晶硅层来完成电容器结构。

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