公开(公告)号：US6038164A

公开(公告)日：2000-03-14

申请号：US200071

申请日：1998-11-25

Applicant: Thomas Schulz ,  Thomas Aeugle ,  Wolfgang Rosner ,  Lothar Risch

Inventor： Thomas Schulz ,  Thomas Aeugle ,  Wolfgang Rosner ,  Lothar Risch

IPC: H01L21/8244 ,  H01L27/11 ,  G11C11/00

CPC classification number: H01L27/11 ,  H01L27/1104

Abstract: The SRAM cell configuration has at least six transistors in each memory cell. Four of the transistors form a flip-flop and they are arranged at the corners of a quadrilateral. The flip-flop is driven by two of the transistors, which are disposed so as to adjoin diagonally opposite corners of the quadrilateral and outside the quadrilateral. Adjacent memory cells along a word line can be arranged in such a way that a first bit line and a second bit line of the adjacent memory cells coincide. The transistors are preferably vertical and are arranged at semiconductor structures (St1, St2, St3, St4, St5, St6) produced from a layer sequence. Two of the transistors having n-doped channel regions are preferably formed in each case on two semiconductor structures.

Abstract translation: SRAM单元配置在每个存储单元中具有至少六个晶体管。 四个晶体管形成触发器，并且它们被布置在四边形的角部。 触发器由两个晶体管驱动，这些晶体管被设置为邻接四边形的对角线相对的角部并且在四边形之外。 沿着字线的相邻存储器单元可以以相邻存储器单元的第一位线和第二位线重合的方式布置。 晶体管优选是垂直的，并且被布置在从层序列产生的半导体结构（St1，St2，St3，St4，St5，St6）处。 在每种情况下，优选在两个半导体结构上形成具有n掺杂沟道区的两个晶体管。

公开(公告)号：US5744393A

公开(公告)日：1998-04-28

申请号：US836175

申请日：1997-04-17

Applicant: Lothar Risch ,  Franz Hofmann ,  Wolfgang Rosner ,  Wolfgang Krautschneider

Inventor： Lothar Risch ,  Franz Hofmann ,  Wolfgang Rosner ,  Wolfgang Krautschneider

IPC: H01L21/8234 ,  H01L21/8246 ,  H01L27/088 ,  H01L27/112 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L27/112

Abstract: A method for production of a read-only-memory cell arrangement having vertical MOS transistors is provided. In order to produce a read-only-memory cell arrangement which has first memory cells having a vertical MOS transistor and second memory cells which do not have a vertical MOS transistor, holes provided with a gate dielectric and a gate electrode are etched in a silicon substrate with a layer sequencing corresponding to a source, a channel and a drain for the first memory cells. Insulation trenches whose separation is preferably equal to their width are produced for insulation of adjacent memory cells.

Abstract translation: PCT No.PCT / DE95 / 01365 Sec。 371日期1997年04月17日 102（e）日期1997年4月17日PCT提交1995年10月5日PCT公布。 出版物WO96 / 13064 日期：1996年5月2日提供具有垂直MOS晶体管的只读存储单元布置方法。 为了产生具有垂直MOS晶体管的第一存储单元和不具有垂直MOS晶体管的第二存储单元的只读存储单元布置，在栅极电介质和栅电极中设置的孔被蚀刻在硅 具有对应于第一存储器单元的源极，沟道和漏极的层序列的衬底。 为了绝缘相邻的存储单元而产生绝缘沟槽，其隔离优选等于其宽度。

公开(公告)号：US5516404A

公开(公告)日：1996-05-14

申请号：US275382

申请日：1994-07-15

Applicant: Ignaz Eisele ,  Harald Gossner ,  Hermann Baumgaertner ,  Lothar Risch

Inventor： Ignaz Eisele ,  Harald Gossner ,  Hermann Baumgaertner ,  Lothar Risch

IPC: H01L21/203 ,  C30B23/02 ,  H01J9/02 ,  H01L21/20 ,  H01L21/28 ,  H01L21/306 ,  H01L29/41

CPC classification number: C30B29/06 ,  C30B23/02 ,  H01J9/025 ,  H01J2201/30426

Abstract: A method for manufacturing an electrically conductive tip for field emission cathodes of vacuum electronic components includes forming the tip of doped silicon by molecular beam epitaxy of doped silicon through an opening of a mask and onto a substrate of monocrystalline silicon. The molecular beam epitaxy also produces a doped silicon layer on the surface of the mask.

Abstract translation: 用于制造真空电子部件的场致发射阴极的导电尖端的方法包括通过掩模的开口通过掺杂硅的分子束外延形成掺杂硅的尖端并到单晶硅的衬底上。 分子束外延还在掩模的表面上产生掺杂的硅层。

公开(公告)号：US4390888A

公开(公告)日：1983-06-28

申请号：US182472

申请日：1980-08-28

Applicant: Lothar Risch ,  Hermann Mader

Inventor： Lothar Risch ,  Hermann Mader

IPC: H04N5/33 ,  H01L27/146 ,  H01L27/148 ,  H01L27/14

CPC classification number: H01L27/14875 ,  H01L27/14649

Abstract: An x-y infrared CCD sensor employing the photoelectric effect as in a p-doped semiconductor substrate of silicon with an n.sup.+ pn diode as the infrared sensor element with a three layer structure in the vertical direction in the semiconductor substrate and a n-channel charge coupled device shift register. The device has a metal-oxide-semiconductor storage electrode directly adjacent to the n-region of the three layer structure. The device is manufactured by masked ion implantation with the doping density for the three layer sequence such that the doping density for the layer operating as the emitter is greater than the doping density for the layer operating as a base, which in turn is greater than the doping density for the layer operating as the collector.

Abstract translation: 使用光电效应的xy红外CCD传感器，其中n + pn二极管的p掺杂半导体衬底中的红外传感器元件在半导体衬底中具有垂直方向的三层结构，并且n沟道电荷耦合 器件移位寄存器。 该器件具有与三层结构的n区直接相邻的金属氧化物半导体存储电极。 该器件通过掩模离子注入制造，具有三层序列的掺杂密度，使得作为发射极工作的层的掺杂密度大于作为基极操作的层的掺杂密度，其又大于 作为收集器操作的层的掺杂密度。

公开(公告)号：US07804708B2

公开(公告)日：2010-09-28

申请号：US12182698

申请日：2008-07-30

Applicant: Ulrike Gruening-von Schwerin ,  Lothar Risch ,  Peter Baars ,  Klaus Muemmler ,  Stefan Tegen ,  Thomas Happ

Inventor： Ulrike Gruening-von Schwerin ,  Lothar Risch ,  Peter Baars ,  Klaus Muemmler ,  Stefan Tegen ,  Thomas Happ

IPC: G11C11/00 ,  G11C5/06 ,  H01L29/02

CPC classification number: G11C13/0004 ,  G11C2213/72 ,  H01L27/24

Abstract: An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.

Abstract translation: 一种包括存储单元阵列和方法的集成电路。 在一个实施例中，每个存储单元包括电阻切换存储器元件和用于从多个存储器单元中选择一个单元的选择二极管。 存储元件与其顶部耦合到第一选择线并且其底侧连接到选择二极管，二极管还耦合到第二选择线的底侧。

公开(公告)号：US06909141B2

公开(公告)日：2005-06-21

申请号：US10047013

申请日：2002-01-16

Applicant: Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Thomas Äugle ,  Herbert Schäfer ,  Martin Franosch

Inventor： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Thomas Äugle ,  Herbert Schäfer ,  Martin Franosch

IPC: H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L21/8238

CPC classification number: B82Y10/00 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/7613 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

Abstract: A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has vertical pillar structures statistically distributed over the substrate. The vertical pillar structures are electrically connected on a base side thereof to a first common electrical contact. The vertical pillar structures include, along the vertical direction, layer zones of differing conductivity, and have insulation layers on their circumferential walls. An electrically conductive material is deposited between the pillar structures and forms a second electrical contact of the semiconductor transistor component. The pillar structures are electrically contacted to a third common electrical contact on their capping side.

Abstract translation: 通过使用统计掩模在衬底上构建垂直半导体晶体管组件。 垂直半导体晶体管组件具有统计分布在衬底上的垂直柱结构。 垂直柱结构在其基极侧电连接到第一公共电接触。 垂直柱结构沿垂直方向包括不同导电性的层区，并且在其周壁上具有绝缘层。 导电材料沉积在柱结构之间并形成半导体晶体管组件的第二电接触。 支柱结构在其封盖侧与第三公共电触头电接触。

公开(公告)号：US06614069B2

公开(公告)日：2003-09-02

申请号：US10054440

申请日：2002-01-22

Applicant: Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Ties Ramcke

Inventor： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Ties Ramcke

IPC: H01L29788

CPC classification number: B82Y10/00 ,  H01L21/28273 ,  H01L29/7887 ,  H01L29/7888

Abstract: A nonvolatile semiconductor memory cell includes a transistor component formed on a substrate and a storage node that determines the switching state of the transistor component. The storage node is arranged near a control gate electrode. The storage node has a group of vertically oriented column structures having at least two semiconductor layer zones and an insulating layer zone situated between the two semiconductor layer zones.

公开(公告)号：US06351408B1

公开(公告)日：2002-02-26

申请号：US09544761

申请日：2000-04-06

Applicant: Siegfried Schwarzl ,  Lothar Risch

Inventor： Siegfried Schwarzl ,  Lothar Risch

IPC: G11C1100

CPC classification number: H01L27/228 ,  G11C11/15 ,  G11C11/16 ,  H01L27/222

Abstract: A memory cell configuration has word lines and bit lines running transversely with respect thereto. Memory elements with a magnetoresistive effect are respectively connected between one of the word lines and one of the bit lines. The memory elements are disposed in at least two layers one above the other.

Abstract translation: 存储单元配置具有相对于其横向延伸的字线和位线。 具有磁阻效应的存储元件分别连接在一条字线和一条位线之间。 存储元件设置在彼此之上的至少两层中。

公开(公告)号：US06300652B1

公开(公告)日：2001-10-09

申请号：US08755456

申请日：1996-11-22

Applicant: Lothar Risch ,  Franz Hofmann ,  Rainer Bruchhaus ,  Wolfram Wersing

Inventor： Lothar Risch ,  Franz Hofmann ,  Rainer Bruchhaus ,  Wolfram Wersing

IPC: H01L27108

CPC classification number: H01L27/11502 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60

Abstract: A memory cell configuration and a method for its production include stacked capacitors and use a vertical storage capacitor having a ferroelectric or paraelectric storage dielectric. In order to produce the storage capacitor, a dielectric layer for the storage dielectric is produced over the whole area. The dielectric layer is subsequently structured and first electrodes and second electrodes for the storage capacitors are formed. The invention is suitable for Gbit DRAMs and for nonvolatile memories.

Abstract translation: 存储单元配置及其制造方法包括堆叠电容器，并且使用具有铁电或顺电存储电介质的垂直存储电容器。 为了制造存储电容器，在整个区域上产生用于存储电介质的电介质层。 随后构造电介质层，形成用于存储电容器的第一电极和第二电极。 本发明适用于Gbit DRAM和非易失性存储器。

公开(公告)号：US06184045B2

公开(公告)日：2001-02-06

申请号：US09541952

申请日：2000-04-03

Applicant: Franz Hofman ,  Lothar Risch ,  Wolfgang Roesner ,  Wolfgang Krautschneider

Inventor： Franz Hofman ,  Lothar Risch ,  Wolfgang Roesner ,  Wolfgang Krautschneider

IPC: H01L218242

CPC classification number: H01L27/10852 ,  H01L27/10808

Abstract: A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis of trenches which are of different widths, which extend transversely to one another, and which are arranged between the first capacitor electrodes. At least a part of each first capacitor electrode can be created from a layer which is structured by the trenches. Trenches can be narrowed by spacers.

Abstract translation: 存储单元包含至少一个晶体管和一个连接到高位线的电容器。 电容器包含布置在晶体管上方的第一电容器电极，并连接到晶体管。 基于具有不同宽度的沟槽彼此横向延伸并且布置在第一电容器电极之间的沟槽可以以自调节的方式创建高位线。 每个第一电容器电极的至少一部分可以由由沟槽构成的层产生。 沟槽可以通过间隔物变窄。