公开(公告)号：US4390888A

公开(公告)日：1983-06-28

申请号：US182472

申请日：1980-08-28

Applicant: Lothar Risch ,  Hermann Mader

Inventor： Lothar Risch ,  Hermann Mader

IPC: H04N5/33 ,  H01L27/146 ,  H01L27/148 ,  H01L27/14

CPC classification number: H01L27/14875 ,  H01L27/14649

Abstract: An x-y infrared CCD sensor employing the photoelectric effect as in a p-doped semiconductor substrate of silicon with an n.sup.+ pn diode as the infrared sensor element with a three layer structure in the vertical direction in the semiconductor substrate and a n-channel charge coupled device shift register. The device has a metal-oxide-semiconductor storage electrode directly adjacent to the n-region of the three layer structure. The device is manufactured by masked ion implantation with the doping density for the three layer sequence such that the doping density for the layer operating as the emitter is greater than the doping density for the layer operating as a base, which in turn is greater than the doping density for the layer operating as the collector.

Abstract translation: 使用光电效应的xy红外CCD传感器，其中n + pn二极管的p掺杂半导体衬底中的红外传感器元件在半导体衬底中具有垂直方向的三层结构，并且n沟道电荷耦合 器件移位寄存器。 该器件具有与三层结构的n区直接相邻的金属氧化物半导体存储电极。 该器件通过掩模离子注入制造，具有三层序列的掺杂密度，使得作为发射极工作的层的掺杂密度大于作为基极操作的层的掺杂密度，其又大于 作为收集器操作的层的掺杂密度。

公开(公告)号：US07180115B1

公开(公告)日：2007-02-20

申请号：US10130441

申请日：2000-11-14

Applicant: Franz Hofmann ,  Wolfgang Roesner ,  Lothar Risch ,  Till Schloesser

Inventor： Franz Hofmann ,  Wolfgang Roesner ,  Lothar Risch ,  Till Schloesser

IPC: H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10867 ,  H01L27/10891 ,  H01L27/1203

Abstract: The invention relates to a transistor that is provided with a first source/drain area (S/D1), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected to the first source/drain area (S/D1). An insulating structure entirely surrounds an insulating area of the circuit arrangement. At least the first capacitor electrode (SP) and the first source/drain area (S/D1) are arranged in the insulating area. The second source/drain area (S/D2) and the second capacitor electrode of the capacitor are arranged outside the insulating area. The insulating structure prevents the first capacitor electrode (SP) from loosing charge through leaking currents between charging and discharging of the capacitor. A tunnel barrier (T) which is arranged in the channel area (KA) is part of the insulating structure. A capacitor dielectric (KD) that separates the first capacitor electrode (SP) from the second capacitor electrode is part of the insulating structure.

Abstract translation: 本发明涉及一种具有第一源极/漏极区域（S / D 1），与其相邻的沟道区域（KA），与其相邻的第二源极/漏极区域（S / D 2），栅极电介质 和栅电极。 电容器的第一电容器电极（SP）连接到第一源极/漏极区域（S / D 1）。 绝缘结构完全围绕电路装置的绝缘区域。 至少第一电容器电极（SP）和第一源极/漏极区域（S / D 1）布置在绝缘区域中。 电容器的第二源极/漏极区域（S / D 2）和第二电容器电极布置在绝缘区域的外部。 绝缘结构防止第一电容器电极（SP）通过电容器的充电和放电之间的泄漏电流而失去电荷。 布置在通道区域（KA）中的隧道势垒（T）是绝缘结构的一部分。 将第一电容器电极（SP）与第二电容器电极分离的电容器电介质（KD）是绝缘结构的一部分。

公开(公告)号：US06600200B1

公开(公告)日：2003-07-29

申请号：US09645762

申请日：2000-08-25

Applicant: Bernhard Lustig ,  Herbert Schäfer ,  Lothar Risch

Inventor： Bernhard Lustig ,  Herbert Schäfer ,  Lothar Risch

IPC: H01L2906

CPC classification number: H01L21/823807 ,  H01L21/74 ,  H01L29/1083

Abstract: A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial layer having a dopant concentration of less than 1017 cm−3 is disposed on a surface of the doped well. Source/drain regions doped by a second conductivity type, opposite to the first conductivity type, and a channel region, are disposed in the epitaxial layer, and their depth is less than or equal to the thickness of the epitaxial layer. A method for fabricating two complementary MOS transistors is also provided.

Abstract translation: MOS晶体管及其制造方法包括在半导体衬底中制造由第一导电类型掺杂的阱。 掺杂浓度小于1017cm-3的外延层设置在掺杂阱的表面上。 由第二导电类型掺杂的与第一导电类型相反的源极/漏极区和沟道区设置在外延层中，并且它们的深度小于或等于外延层的厚度。 还提供了制造两个互补MOS晶体管的方法。

公开(公告)号：US06553157B2

公开(公告)日：2003-04-22

申请号：US10093320

申请日：2002-03-07

Applicant: Thomas Schultz ,  Wolfgang Rösner ,  Lothar Risch

Inventor： Thomas Schultz ,  Wolfgang Rösner ,  Lothar Risch

IPC: G02B612

CPC classification number: H01L31/0232 ,  H01L27/1443

Abstract: In an integrated optoelectronic microelectronic system, an optoelectronically active diode part is formed in a semiconductor substrate by zones forming depletion layers. The system is provided in a mesa that stands vertically on a semiconductor substrate and runs in a direction of extension thereof. A light waveguide is optically coupled to the diode part in such a way that light is coupled into the diode part via the mesa side wall.

公开(公告)号：US06518628B1

公开(公告)日：2003-02-11

申请号：US09423864

申请日：1999-11-15

Applicant: Wolfgang Krautschneider ,  Franz Hofmann ,  Lothar Risch

Inventor： Wolfgang Krautschneider ,  Franz Hofmann ,  Lothar Risch

IPC: H01L2976

CPC classification number: H01L27/0922

Abstract: An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.

Abstract translation: 一种集成CMOS电路装置及其制造方法，其包括第一MOS晶体管和与其互补的第二MOS晶体管，其中MOS晶体管中的一个布置在沟槽的底部，而另一个布置在主表面 的半导体衬底。 MOS晶体管相对于彼此布置，使得流过MOS晶体管的电流分别基本上平行于布置在MOS晶体管之间的沟槽的侧壁。

公开(公告)号：US06255684B1

公开(公告)日：2001-07-03

申请号：US09071798

申请日：1998-05-04

Applicant: Wolfgang Roesner ,  Lothar Risch ,  Franz Hofmann

Inventor： Wolfgang Roesner ,  Lothar Risch ,  Franz Hofmann

IPC: H01L27108

CPC classification number: H01L27/10864 ,  H01L27/10841

Abstract: A DRAM cell configuration includes a vertical MOS transistor per memory cell. First source/drain regions of the transistor each belong to two adjacent transistors and adjoin a bit line. Second source/drain regions of the transistor are connected to a storage node. A gate electrode of the transistor has exactly two sides adjoined by a gate oxide. The DRAM cell configuration can be produced by using three masks, with a memory cell area of 4 F2. F is a minimum structure size which can be produced by using the respective technology.

Abstract translation: DRAM单元配置包括每个存储单元的垂直MOS晶体管。 晶体管的第一源极/漏极区域分别属于两个相邻的晶体管并与位线相邻。 晶体管的第二源/漏区连接到存储节点。 晶体管的栅电极具有由栅极氧化物邻接的正好两侧。 可以通过使用具有4F2的存储单元面积的三个掩模来产生DRAM单元配置。 F是可以通过使用各自技术制造的最小结构尺寸。

公开(公告)号：US6037209A

公开(公告)日：2000-03-14

申请号：US254696

申请日：1999-03-15

Applicant: Wolfgang Rosner ,  Lothar Risch ,  Franz Hofmann ,  Reinhard Stengl

Inventor： Wolfgang Rosner ,  Lothar Risch ,  Franz Hofmann ,  Reinhard Stengl

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10823

Abstract: The DRAM cell arrangement comprises, per memory cell, a vertical MOS transistor whose first source/drain region is connected to a storage node of a storage capacitor, whose channel region (3) is annularly enclosed by a gate electrode (13) and whose second source/drain region is connected to a buried bit line. The DRAM cell arrangement is produced using only two masks, with the aid of a spacer technique, with a memory cell area of 2F.sup.2, where F is the minimum structure size which can be produced using the respective technology.

Abstract translation: PCT No.PCT / DE97 / 01580 Sec。 371 1999年3月15日 102（e）1999年3月15日PCT 1997年7月28日PCT公布。 出版物WO98 / 11604 日期1998年3月19日DRAM单元布置包括每个存储单元的垂直MOS晶体管，其第一源极/漏极区域连接到存储电容器的存储节点，其沟道区域（3）被栅电极环形封闭 13），并且其第二源极/漏极区域连接到掩埋位线。 借助于间隔器技术，仅使用两个掩模来制造DRAM单元布置，存储单元面积为2F2，其中F是可以使用各自技术产生的最小结构尺寸。

公开(公告)号：US4966859A

公开(公告)日：1990-10-30

申请号：US293567

申请日：1989-01-03

Applicant: Lothar Risch ,  Reinhard Tielert ,  Wolfgang Mueller ,  Christoph Werner

Inventor： Lothar Risch ,  Reinhard Tielert ,  Wolfgang Mueller ,  Christoph Werner

IPC: H01L21/265 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L29/105 ,  H01L29/78 ,  Y10S148/126

Abstract: A voltage-stable sub-.mu.m-MOS transistor for VLSI circuits consist of a low-resistant silicon substrate of a first conductivity type with a high-resistant, thin, epitaxial layer of the first conductivity type situated thereon and on which a gate electrode consisting of polysilicon is disposed. Highly doped source/drain zones of the second conductivity type form a channel region of the first conductivity type. A doping substance concentration, rising in the direction of the substrate, is generated by means of double implantation, whereby the concentration maximum extends to behind the source/drain zones. A method for manufacturing same incorporates steps of forming the several layers, applying a mask, executing a double implantation in the channel region, and forming the gate electrode.

Abstract translation: 用于VLSI电路的稳压子MOS-MOS晶体管由具有第一导电类型的低电阻硅衬底和位于其上的第一导电类型的高电阻，薄外延层组成，栅电极 由多晶硅组成。 第二导电类型的高掺杂源/漏区形成第一导电类型的沟道区。 通过双重注入产生沿衬底方向上升的掺杂物质浓度，由此浓度最大值延伸到源极/漏极区之后。 其制造方法包括形成几层的步骤，施加掩模，在沟道区域中执行双注入，以及形成栅电极。

公开(公告)号：US4823180A

公开(公告)日：1989-04-18

申请号：US437302

申请日：1982-10-28

Applicant: Armin Wieder ,  Lothar Risch

Inventor： Armin Wieder ,  Lothar Risch

IPC: H01L31/10 ,  H01L29/04 ,  H01L31/113 ,  H01L27/14

CPC classification number: H01L29/04 ,  H01L31/1136

Abstract: A photo-transistor in MOS thin-film technology operable with alternating voltages is comprised of a semiconductor body (3) composed of polycrystalline silicon having source (4) and drain (5) zones therein spaced apart by an undoped channel region (13) and having a gate electrode (1, 10) separated from the semiconductor body (3) by a SiO.sub.2 layer (2) produced by thermal oxidation. These phototransistors are easily and reproducably produced and are characterized by low threshold voltages and a good transistor characteristic curve. Thus, these photo-transistors are well suited for use as sensor elements, opto-couplers, time-delay elements and as photo-transistors in VLSI circuits.

Abstract translation: 可以用交流电压工作的MOS薄膜技术的光电晶体管由半导体本体（3）组成，半导体本体（3）由多晶硅构成，多晶硅具有由未掺杂沟道区（13）间隔的源极（4）和漏极（5） 具有通过由热氧化产生的SiO 2层（2）与半导体本体（3）分离的栅电极（1,10）。 这些光电晶体管容易且可再生产，其特征在于低阈值电压和良好的晶体管特性曲线。 因此，这些光电晶体管非常适合用作VLSI电路中的传感器元件，光耦合器，延时元件和光电晶体管。

公开(公告)号：US07829892B2

公开(公告)日：2010-11-09

申请号：US11926653

申请日：2007-10-29

Applicant: Richard Johannes Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Roesner ,  Till Schloesser ,  Michael Specht

Inventor： Richard Johannes Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Roesner ,  Till Schloesser ,  Michael Specht

IPC: H01L29/12

CPC classification number: H01L27/10823 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10891 ,  H01L29/7851

Abstract: An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.

Abstract translation: 公开了一种包括栅电极的集成电路。 一个实施例提供一种晶体管，其包括第一源极/漏极电极和第二源极/漏极电极。 在半导体衬底中的第一和第二源极/漏极之间布置有沟道。 栅电极被布置在沟道层附近并且与沟道层电绝缘。 半导体基板电极设置在后侧。 栅极电极将沟道层包围至少两个相对的侧面。