公开(公告)号：US20050272270A1

公开(公告)日：2005-12-08

申请号：US11109240

申请日：2005-04-18

Applicant: Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Uday Shah ,  Robert Chau

Inventor： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Uday Shah ,  Robert Chau

IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/51 ,  H01L21/469

CPC classification number: H01L21/28194 ,  H01L21/3105 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/11 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for making a semiconductor device is described. That method comprises modifying a first surface, and forming a high-k gate dielectric layer on an unmodified second surface.

公开(公告)号：US20050266619A1

公开(公告)日：2005-12-01

申请号：US10855635

申请日：2004-05-26

Applicant: Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Uday Shah ,  Chris Barns ,  Suman Datta ,  Robert Turkot ,  Robert Chau

Inventor： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Uday Shah ,  Chris Barns ,  Suman Datta ,  Robert Turkot ,  Robert Chau

IPC: H01L21/00 ,  H01L21/326 ,  H01L21/336 ,  H01L21/479 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871

Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a first gate dielectric layer that has a first substantially vertical component, then forming a first metal layer on the first gate dielectric layer. After forming on the substrate a second gate dielectric layer that has a second substantially vertical component, a second metal layer is formed on the second gate dielectric layer. In this method, a conductor is formed that contacts both the first metal layer and the second metal layer.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成具有第一基本垂直分量的第一栅极电介质层，然后在第一栅极电介质层上形成第一金属层。 在衬底上形成具有第二基本垂直分量的第二栅介质层之后，在第二栅介质层上形成第二金属层。 在该方法中，形成与第一金属层和第二金属层接触的导体。

公开(公告)号：US20050218372A1

公开(公告)日：2005-10-06

申请号：US10816539

申请日：2004-04-01

Applicant: Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Robert Chau

Inventor： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Robert Chau

IPC: B44C1/22 ,  C09K13/00 ,  C09K13/06 ,  H01L21/302 ,  H01L21/3213

CPC classification number: H01L21/32134 ,  C09K13/06

Abstract: Semiconductor integrated circuit structures, such as stacks containing metal layers, may be etched with a modified viscosity etchant. An increased viscosity etchant, for example, may reduce undercutting when a metal film is being etched.

公开(公告)号：US20050214987A1

公开(公告)日：2005-09-29

申请号：US10809853

申请日：2004-03-24

Applicant: Uday Shah ,  Chris Barns ,  Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Robert Chau

Inventor： Uday Shah ,  Chris Barns ,  Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Robert Chau

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/84

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L29/66545

Abstract: A method for making a semiconductor device is described. That method comprises forming a polysilicon layer on a dielectric layer, which is formed on a substrate. The polysilicon layer is etched to generate a patterned polysilicon layer with an upper surface that is wider than its lower surface. The method may be applied, when using a replacement gate process to make transistors that have metal gate electrodes.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在形成在基板上的电介质层上形成多晶硅层。 蚀刻多晶硅层以产生具有比其下表面更宽的上表面的图案化多晶硅层。 当使用替换栅极工艺来制造具有金属栅电极的晶体管时，可以应用该方法。

公开(公告)号：US20050148136A1

公开(公告)日：2005-07-07

申请号：US10748559

申请日：2003-12-29

Applicant: Justin Brask ,  Mark Doczy ,  Jack Kavalieros ,  Matthew Metz ,  Chris Barns ,  Uday Shah ,  Suman Datta ,  Christopher Thomas ,  Robert Chau

Inventor： Justin Brask ,  Mark Doczy ,  Jack Kavalieros ,  Matthew Metz ,  Chris Barns ,  Uday Shah ,  Suman Datta ,  Christopher Thomas ,  Robert Chau

IPC: H01L21/8238 ,  H01L23/48

CPC classification number: H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/1203 ,  H01L29/4975 ,  H01L29/66545 ,  Y10S438/926

Abstract: A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.

Abstract translation: 对半导体装置及其形成方法进行说明。 半导体器件包括形成在衬底的第一部分上的金属NMOS栅电极和形成在衬底的第二部分上的硅化物PMOS栅电极。

公开(公告)号：US20050110072A1

公开(公告)日：2005-05-26

申请号：US11018015

申请日：2004-12-20

Applicant: Justin Brask ,  Mark Doczy ,  Matthew Metz ,  John Barnak ,  Paul Markworth

Inventor： Justin Brask ,  Mark Doczy ,  Matthew Metz ,  John Barnak ,  Paul Markworth

IPC: H01L21/3063 ,  H01L21/28 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/76

CPC classification number: H01L21/28123 ,  H01L21/31111

Abstract: A high-K thin film patterning solution is disclosed to address structural and process limitations of conventional patterning techniques. Subsequent to formation of gate structures adjacent a high-K dielectric layer, a portion of the high-K dielectric layer material is reduced, preferably via exposure to hydrogen gas, to form a reduced portion of the high-K dielectric layer. The reduced portion may be selectively removed utilizing wet etch chemistries to leave behind a trench of desirable geometric properties.

公开(公告)号：US20050101113A1

公开(公告)日：2005-05-12

申请号：US10704497

申请日：2003-11-06

Applicant: Justin Brask ,  Mark Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew Metz ,  Robert Chau ,  Robert Turkot

Inventor： Justin Brask ,  Mark Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew Metz ,  Robert Chau ,  Robert Turkot

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/3205

CPC classification number: H01L29/4958 ,  H01L21/28079 ,  H01L21/32134 ,  H01L21/823842

Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, and forming a first metal layer on a first part of the dielectric layer, leaving a second part of the dielectric layer exposed. After a second metal layer is formed on both the first metal layer and the second part of the dielectric layer, a masking layer is formed on the second metal layer.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成电介质层，并且在介电层的第一部分上形成第一金属层，留下介电层的第二部分露出。 在第一金属层和电介质层的第二部分上形成第二金属层之后，在第二金属层上形成掩模层。

公开(公告)号：US20050048794A1

公开(公告)日：2005-03-03

申请号：US10652796

申请日：2003-08-28

Applicant: Justin Brask ,  Mark Doczy ,  Scott Hareland ,  John Barnak ,  Matthew Metz ,  Jack Kavalieros ,  Robert Chau

Inventor： Justin Brask ,  Mark Doczy ,  Scott Hareland ,  John Barnak ,  Matthew Metz ,  Jack Kavalieros ,  Robert Chau

IPC: H01L21/28 ,  H01L21/30 ,  H01L21/306 ,  H01L21/316 ,  H01L29/51 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/02244 ,  H01L21/02052 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/3003 ,  H01L21/31612 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31683 ,  H01L21/31691 ,  H01L29/513 ,  H01L29/517

Abstract: A method for making a semiconductor device is described. That method comprises forming a metal oxide layer on a substrate, converting at least part of the metal oxide layer to a metal layer; and oxidizing the metal layer to generate a metal oxide high-k gate dielectric layer.

公开(公告)号：US09461160B2

公开(公告)日：2016-10-04

申请号：US13976837

申请日：2011-12-19

Applicant: Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/7787 ,  G06F1/1633 ,  G06F1/189 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789 ,  H01L29/785 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451

Abstract: Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (1010) plane on a (110) plane of the silicon.

Abstract translation: 用于高压和高频工作的晶体管。 具有设置在第一和第二相对侧壁之间的顶表面的非平面极性晶体半导体本体包括具有设置在第一和第二侧壁上的第一晶体半导体层的沟道区域。 第一晶体半导体层是在沟道区内提供二维电子气（2DEG）。 栅极结构沿至少第二侧壁设置在第一晶体半导体层上方，以调制2DEG。 非平面极性结晶半导体主体的第一和第二侧壁可具有不同的极性，其中通道靠近第一侧壁。 栅极结构可以沿着侧壁中的第二侧面以栅极背栅。 极性结晶半导体体可以是在硅衬底上形成的III族氮化物，其中（1010）面在硅的（110）平面上。

公开(公告)号：US20140175509A1

公开(公告)日：2014-06-26

申请号：US13723563

申请日：2012-12-21

Applicant: BENJAMIN CHU-KUNG ,  VAN LE ,  ROBERT CHAU ,  SANSAPTAK DASGUPTA ,  GILBERT DEWEY ,  NITI GOEL ,  JACK KAVALIEROS ,  MATTHEW METZ ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  WILLY RACHMADY ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  NANCY ZELICK

Inventor： BENJAMIN CHU-KUNG ,  VAN LE ,  ROBERT CHAU ,  SANSAPTAK DASGUPTA ,  GILBERT DEWEY ,  NITI GOEL ,  JACK KAVALIEROS ,  MATTHEW METZ ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  WILLY RACHMADY ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  NANCY ZELICK

IPC: H01L29/06

CPC classification number: H01L29/7391 ,  H01L29/0676 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66356 ,  H01L29/66393 ,  H01L29/732 ,  H01L29/735 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7436 ,  H01L29/785

Abstract: An embodiment concerns forming an EPI film on a substrate where the EPI film has a different lattice constant from the substrate. The EPI film and substrate may include different materials to collectively form a hetero-epitaxial device having, for example, a Si and/or SiGe substrate and a III-V or IV film. The EPI film may be one of multiple EPI layers or films and the films may include different materials from one another and may directly contact one another. Further, the multiple EPI layers may be doped differently from another in terms of doping concentration and/or doping polarity. One embodiment includes creating a horizontally oriented hetero-epitaxial structure. Another embodiment includes a vertically oriented hetero-epitaxial structure. The hetero-epitaxial structures may include, for example, a bipolar junction transistor, heterojunction bipolar transistor, thyristor, and tunneling field effect transistor among others. Other embodiments are described herein.

Abstract translation: 一个实施例涉及在衬底上形成EPI膜，其中EPI膜具有与衬底不同的晶格常数。 EPI膜和衬底可以包括不同的材料以共同形成具有例如Si和/或SiGe衬底和III-V或IV膜的异质外延装置。 EPI膜可以是多个EPI层或膜中的一个，并且膜可以包括彼此不同的材料并且可以直接彼此接触。 此外，在掺杂浓度和/或掺杂极性方面，多个EPI层可以与另一个不同地被掺杂。 一个实施例包括产生水平取向的异质外延结构。 另一实施例包括垂直取向的异质外延结构。 异质外延结构可以包括例如双极结型晶体管，异质结双极晶体管，晶闸管和隧道场效应晶体管等。 本文描述了其它实施例。