公开(公告)号：US6096664A

公开(公告)日：2000-08-01

申请号：US130324

申请日：1998-08-06

Applicant: Thomas S. Rupp ,  Stephan Kudelka ,  Jeffrey Gambino ,  Mary Weybright

Inventor： Thomas S. Rupp ,  Stephan Kudelka ,  Jeffrey Gambino ,  Mary Weybright

IPC: H01L21/308 ,  H01L21/334 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823462

Abstract: A method for forming a pair of MOSFETs in different electrically isolated regions of a silicon substrate. Each one of the MOSFETs has a different gate oxide thickness. A first layer of silicon dioxide is grown to a predetermined thickness over the surface of the silicon substrate. One portion of the silicon dioxide layer is over a first isolated region and another portion of the silicon dioxide layer being over a second isolated region. An inorganic layer is formed over the silicon dioxide layer extending over the isolated regions of the silicon substrate. A first portion of the inorganic layer is over the first isolated regions and a second portion of the inorganic layer is over the second isolated regions. A photoresist layer is formed over the inorganic layer. The photoresist layer is patterned with a window over the first portion of the inorganic layer. The photoresist layer covers the second portion of the inorganic layer. The inorganic layer is patterned into an inorganic mask by bringing a etch into contact with the patterned photoresist layer to selectively remove the first portion of the inorganic layer an thereby expose an underlying portion of the surface of the silicon substrate while leaving the second portion of the inorganic layer. The inorganic mask is used to selectively remove exposed portions of the grown silicon dioxide. The inorganic mask is removed. A second layer of silicon dioxide is grown over the exposed underlying portion of the silicon substrate to a thickness different from the thickness of the first layer of silicon dioxide. The silicon dioxide layers are patterned into gate oxides for each of a corresponding one of the pair of MOSFETs.

Abstract translation: 一种用于在硅衬底的不同电隔离区域中形成一对MOSFET的方法。 每个MOSFET具有不同的栅极氧化物厚度。 在硅衬底的表面上生长第一层二氧化硅至预定厚度。 二氧化硅层的一部分在第一隔离区上方，二氧化硅层的另一部分在第二隔离区之上。 在硅衬底的隔离区域上延伸的二氧化硅层之上形成无机层。 无机层的第一部分在第一隔离区之上，无机层的第二部分在第二隔离区之上。 在无机层上形成光致抗蚀剂层。 在无机层的第一部分上的窗口对光致抗蚀剂层进行图案化。 光致抗蚀剂层覆盖无机层的第二部分。 通过使蚀刻与图案化的光致抗蚀剂层接触来将无机层图案化成无机掩模，以选择性地去除无机层的第一部分，从而暴露硅衬底的表面的下面部分，同时留下第二部分的 无机层。 无机掩模用于选择性地去除生长的二氧化硅的暴露部分。 去除无机掩模。 第二层二氧化硅在硅衬底的暴露下面的部分上生长到与第一层二氧化硅的厚度不同的厚度。 将二氧化硅层图案化成对于一对MOSFET中的每一个的栅极氧化物。

公开(公告)号：US6066527A

公开(公告)日：2000-05-23

申请号：US361055

申请日：1999-07-26

Applicant: Stephan Kudelka ,  Alexander Michaelis

Inventor： Stephan Kudelka ,  Alexander Michaelis

IPC: H01L21/306 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10861

Abstract: In accordance with the present invention, a method for etching back filler material for a buried strap for deep trench capacitors includes the steps of forming a trench in a substrate, filling the trench with a first filler material, recessing the first filler material to a predetermined depth relative to a dielectric collar formed in the trench, forming a divot by etching back the dielectric collar, depositing a liner over the first filler material and portions of the substrate exposed by the formation of the trench, and depositing a second filler material on the liner. A surface of the second filler material is prepared by etching the surface with a wet etchant to provide a hydrogen terminated silicon surface. Wet etching the second filler material is performed to etch back the second filler material selective to the liner and the substrate. The second filler material is etched to form a buried strap.

Abstract translation: 根据本发明，用于深沟槽电容器的掩埋带的填充材料的回填方法包括以下步骤：在衬底中形成沟槽，用第一填充材料填充沟槽，将第一填充材料凹入预定的 相对于形成在沟槽中的介电轴颈的深度，通过蚀刻回介质轴环，在第一填充材料上沉积衬垫和衬底的部分通过形成沟槽而暴露的衬底，并将沉积第二填料 衬垫。 通过用湿蚀刻剂蚀刻该表面以提供氢封端的硅表面来制备第二填料的表面。 执行湿蚀刻第二填充材料以蚀刻对衬垫和衬底有选择性的第二填充材料。 第二填充材料被蚀刻以形成掩埋带。

公开(公告)号：US20080176375A1

公开(公告)日：2008-07-24

申请号：US11970654

申请日：2008-01-08

Applicant: Elke Erben ,  Stephan Kudelka ,  Alfred Kersch ,  Angela Link ,  Matthias Patz ,  Jonas Sundqvist

Inventor： Elke Erben ,  Stephan Kudelka ,  Alfred Kersch ,  Angela Link ,  Matthias Patz ,  Jonas Sundqvist

IPC: H01L21/31 ,  H01L21/02

CPC classification number: H01L21/3141 ,  C23C16/0272 ,  C23C16/405 ,  C23C16/45553 ,  H01L21/0228 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/40

Abstract: The present invention relates to a deposition of a dielectric layer. On a substrate having a structured area a crystallization seed layer for a dielectric layer is deposited via an atomic layer deposition technique employing a first and a second precursor on the structured area of the substrate. The first pre-cursor is a compound having the constitutional formula M1(R1Cp)x(R2)4-x, wherein M1 is one of hafnium and zirconium, Cp is cyclopentadienyl, R1 is independently selected of methyl, ethyl and alkyl, R2 is independently selected of hydrogen, methyl, ethyl, alkyl and alkoxyl, and x is one or two. The dielectric layer is deposited on the crystallization seed layer via an atomic layer deposition technique employing a third and a forth precursor wherein the third pre-cursor being a compound having the constitutional formula M2 R3 R4 R5 R6, wherein M2 is one of hafnium or zirconium and R3, R4, R5, and R6 are independently selected of alkyl amines.

Abstract translation: 本发明涉及电介质层的沉积。 在具有结构区域的基板上，通过使用第一和第二前体的原子层沉积技术在基板的结构化区域上沉积用于电介质层的结晶种子层。 第一个前体是具有结构式M 1（R 1）的化合物，其中R 1，R 2，R 2， 其中M 1是铪和锆中的一种，Cp是环戊二烯基，R 1独立地选自甲基，乙基 和烷基，R 2独立地选自氢，甲基，乙基，烷基和烷氧基，x是一个或两个。 介电层通过使用第三和第四前体的原子层沉积技术沉积在结晶种子层上，其中第三个前体是具有结构式M 2 O 3的化合物 其中M 2是铪或锆中的一种，R 2是R 5 R 4，R 5，R 6和R 6独立地选自烷基胺。

公开(公告)号：US20080173919A1

公开(公告)日：2008-07-24

申请号：US11655583

申请日：2007-01-19

Applicant: Stephan Kudelka ,  Lars Oberbeck ,  Uwe Schroeder ,  Tim Boescke ,  Johannes Heitmann ,  Annette Saenger ,  Joerg Schumann ,  Elke Erben

Inventor： Stephan Kudelka ,  Lars Oberbeck ,  Uwe Schroeder ,  Tim Boescke ,  Johannes Heitmann ,  Annette Saenger ,  Joerg Schumann ,  Elke Erben

IPC: G11C11/24 ,  B05D5/12 ,  H01G9/00

CPC classification number: H01L21/02181 ,  H01G4/10 ,  H01G4/33 ,  H01L21/02189 ,  H01L21/3141 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10852 ,  H01L28/65

Abstract: The present invention relates to a method for depositing a dielectric material comprising a transition metal compound. After providing a substrate, a first pre-cursor comprising a transition metal compound and a second pre-cursor predominantly comprising at least one of water vapour, ammonia and hydrazine are successively applied on the substrate for forming a first layer of transition metal containing material. In a next step the first pre-cursor and a third pre-cursor comprising at least one of ozone and oxygen are successively applied on the first layer for forming a second layer of the transition metal containing material.

Abstract translation: 本发明涉及沉积包含过渡金属化合物的电介质材料的方法。 在提供衬底之后，在衬底上依次施加包含过渡金属化合物的第一前体和主要包含水蒸汽，氨和肼中的至少一种的第二前体，形成含第一层含过渡金属的材料。 在下一步骤中，在第一层上依次施加包含臭氧和氧气中的至少一种的第一前视标和第三前标，以形成含过渡金属的材料的第二层。

公开(公告)号：US20070059893A1

公开(公告)日：2007-03-15

申请号：US11518504

申请日：2006-09-07

Applicant: Stephan Kudelka ,  Peter Moll ,  Stefan Jakschik ,  Odo Wunnicke

Inventor： Stephan Kudelka ,  Peter Moll ,  Stefan Jakschik ,  Odo Wunnicke

IPC: H01L21/336

CPC classification number: H01L28/90 ,  H01L27/10814 ,  H01L27/10852

Abstract: A method produces stacked capacitors for dynamic memory cells, in which a number of trenches (48) are formed in the masking layer (40), each trench (48) being arranged above a respective contact plug (26) and extending from the top (42) of the masking layer (40) to the contact plugs (26). A conductive layer (50) covers the side walls (49) of the trenches (48) and the contact plugs (26) in order to form a first electrode (60) of a stacked capacitor (12). In an upper region (63), which is remote from the contact stack (26), the conductive layer (50) is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.

Abstract translation: 一种方法产生用于动态存储单元的堆叠电容器，其中在掩模层（40）中形成有多个沟槽（48），每个沟槽（48）布置在相应的接触插塞（26）的上方并从顶部 屏蔽层（40）的至少部分（42）连接到接触插塞（26）。 为了形成叠层电容器（12）的第一电极（60），导电层（50）覆盖沟槽（48）的侧壁（49）和接触插塞（26）。 在远离接触堆叠（26）的上部区域（63）中，导电层（50）由绝缘层代替，使得在任何粘附的情况下不可能出现短路 在相邻电极之间。

公开(公告)号：US20060128128A1

公开(公告)日：2006-06-15

申请号：US11296568

申请日：2005-12-08

Applicant: Bernd Hintze ,  Stephan Kudelka ,  Jonas Sundqvist

Inventor： Bernd Hintze ,  Stephan Kudelka ,  Jonas Sundqvist

IPC: H01L21/20

CPC classification number: H01L28/60 ,  H01L21/3141 ,  H01L21/318 ,  H01L21/76846

Abstract: In a method for producing a conductive layer a substrate is provided. On the substrate, a layer comprised of at least two different metal nitrides is provided. Especially, on a surface of the substrate a first metal nitride layer, on a surface of the first metal nitride layer a second metal nitride layer, and on a surface of the second metal nitride layer a third metal nitride layer is deposited.

Abstract translation: 在制造导电层的方法中，提供了基板。 在衬底上提供由至少两种不同的金属氮化物组成的层。 特别地，在基板的表面上，沉积第一金属氮化物层，在第一金属氮化物层的表面上具有第二金属氮化物层，并且在第二金属氮化物层的表面上沉积第三金属氮化物层。

公开(公告)号：US20060003536A1

公开(公告)日：2006-01-05

申请号：US11152968

申请日：2005-06-15

Applicant: Stephan Kudelka

Inventor： Stephan Kudelka

IPC: H01L21/76 ,  H01L21/20

CPC classification number: H01L27/10867

Abstract: The present invention provides a method for fabricating a trench capacitor with an insulation collar (10) in a substrate (1), which is electrically connected to the substrate (1) on one side via a buried contact, having the steps of: providing a trench (5) in the substrate (1) using a hard mask (2, 3) with a corresponding mask opening; providing a capacitor dielectric (30) in the lower and central trench region, the insulation collar (10) in the central and upper trench region and an electrically conductive filling (20) as far as the top side of the insulation collar (10); providing a spacer (21′) made of a conductive material above the insulation collar (10) in electrical contact with the substrate (1); completely filling the trench (5) with a filling material (23; 50) above the liner layer (22; 40); carrying out an STI trench fabrication process; removing the filling material (23; 50) and sinking the electrically conductive filling (20) to below the top side of the insulation collar (10); providing a metallic filling (25) in the trench (5) and etching back the metallic filling (25) as far as the top side of the spacer (21′); and providing an insulation region (IS) on one side and a contact region (KS) on a different side with respect to the substrate (1) above the insulation collar (10) by partly removing the spacer (21′).

Abstract translation: 本发明提供一种制造具有衬底（1）中的绝缘套环（10）的沟槽式电容器的方法，该衬底（1）通过埋入触点在一侧电连接到衬底（1），具有以下步骤：提供 使用具有对应的掩模开口的硬掩模（2,3）在基板（1）中的沟槽（5） 在所述下部和中部沟槽区域中设置电容器电介质（30），所述中间和上部沟槽区域中的所述绝缘套环（10）和至少所述绝缘套环（10）的顶侧的导电填充物（20）; 提供由绝缘套环（10）上方的导电材料制成的与衬底（1）电接触的间隔物（21'）; 用衬垫层（22; 40）上方的填充材料（23; 50）完全填充沟槽（5）; 进行STI沟槽制作工艺; 移除所述填充材料（23; 50）并将所述导电填料（20）下沉到所述绝缘套环（10）的顶侧的下方; 在所述沟槽（5）中提供金属填充物（25）并且将所述金属填充物（25）蚀刻回所述间隔物（21'）的顶侧; 并且通过部分地移除间隔件（21'），在绝缘套环（10）的上方在相对于衬底（1）的不同侧上提供绝缘区域（IS）和接触区域（KS）。

公开(公告)号：US20050245025A1

公开(公告)日：2005-11-03

申请号：US11150142

申请日：2005-06-13

Applicant: Stephan Kudelka

Inventor： Stephan Kudelka

IPC: C25F3/12 ,  H01L21/20 ,  H01L21/3063 ,  H01L21/82 ,  H01L21/8242

CPC classification number: H01L27/1087 ,  C25F3/12 ,  H01L21/3063

Abstract: A method of forming trench capacitors in, e. g., a DRAM device, using an electrochemical etch with built-in etch stop to fabricate well-defined bottle-shaped capacitors is described. The process includes formation of a sacrificial silicon layer after initial deep trench formation, wherein the sacrificial layer is formed by doping, and upon its removal, a bottle trench is formed. A second region of doped silicon located below the sacrificial layer is resistant to the chemical etch performed to remove the sacrificial layer, and thereby renders the bottle trench formation process self-limiting.

Abstract translation: 一种形成沟槽电容器的方法， 描述了使用具有内置蚀刻停止件的电化学蚀刻来制造明确定义的瓶形电容器的DRAM器件。 该过程包括在初始深沟槽形成之后形成牺牲硅层，其中牺牲层通过掺杂形成，并且在其去除时形成瓶沟槽。 位于牺牲层下方的掺杂硅的第二区域对于去除牺牲层而进行的化学蚀刻是耐受的，从而使瓶形成沟槽形成过程是自限制的。

公开(公告)号：US20050167741A1

公开(公告)日：2005-08-04

申请号：US10770264

申请日：2004-02-02

Applicant: Ramachandra Divakaruni ,  Stephan Kudelka ,  Jack Mandelman

Inventor： Ramachandra Divakaruni ,  Stephan Kudelka ,  Jack Mandelman

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/06 ,  H01L29/423 ,  H01L29/737 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/66537 ,  H01L21/28114 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/0692 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7371 ,  H01L29/7834

Abstract: Semiconductor devices having improved isolation are provided along with methods of fabricating such semiconductor devices. The improved isolation includes an encapsulated spacer formed within a gate region of a device.

Abstract translation: 提供具有改进的隔离的半导体器件与制造这种半导体器件的方法一起提供。 改进的隔离包括形成在器件的栅极区域内的封装间隔物。

公开(公告)号：US06613642B2

公开(公告)日：2003-09-02

申请号：US10016075

申请日：2001-12-13

Applicant: Stephen Rahn ,  Irene McStay ,  Helmut Horst Tews ,  Uwe Schroeder ,  Stephan Kudelka ,  Rajarao Jammy

Inventor： Stephen Rahn ,  Irene McStay ,  Helmut Horst Tews ,  Uwe Schroeder ,  Stephan Kudelka ,  Rajarao Jammy

IPC: H01L2120

CPC classification number: H01L27/1087 ,  H01L28/84 ,  H01L28/90

Abstract: A method for increasing the surface area of an original surface in a semiconductor device is disclosed. In an exemplary embodiment of the invention, the method includes forming a layered mask upon the original surface, the layered mask including a masking layer thereatop having a varying thickness. An isotropic etch is then applied to the layered mask, which isotropic etch further removes exposed portions of the original surface as the layered mask is removed. Thereby, the isotropic etch enhances the non-uniformity of the masking layer and creates a non-uniformity in planarity of the original surface.

Abstract translation: 公开了一种用于增加半导体器件中原始表面的表面积的方法。 在本发明的示例性实施例中，该方法包括在原始表面上形成分层掩模，该分层掩模包括具有变化厚度的掩模层。 然后将各向同性蚀刻施加到分层掩模，其中各向同性蚀刻在去除层状掩模时进一步去除原始表面的暴露部分。 因此，各向同性蚀刻增强了掩模层的不均匀性并且产生了原始表面的平坦度的不均匀性。