公开(公告)号：US20050206004A1

公开(公告)日：2005-09-22

申请号：US11128493

申请日：2005-05-13

Applicant: Stephan Cohen ,  Stephen Gates ,  Jeffrey Hedrick ,  Elbert Huang ,  Dirk Pfeiffer

Inventor： Stephan Cohen ,  Stephen Gates ,  Jeffrey Hedrick ,  Elbert Huang ,  Dirk Pfeiffer

IPC: H01L20060101 ,  H01L21/00 ,  H01L21/312 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L21/02282 ,  H01L21/02126 ,  H01L21/02222 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3125 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/31663 ,  H01L2924/00

Abstract: The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween, where the ceramic diffusion barrier has a composition SivNwCxOyHz, where 0.1≦v≦0.9, 0≦w≦0.5, 0.01≦x≦0.9, 0≦y≦0.7, 0.01≦z≦0.8 for v+w+x+y+z=1. The ceramic diffusion barrier acts as a diffusion barrier to metals, i.e., copper. The present invention also comprises a method for forming the inventive ceramic diffusion barrier including the steps depositing a polymeric preceramic having a composition SivNwCxOyHz, where 0.1

公开(公告)号：US20050186778A1

公开(公告)日：2005-08-25

申请号：US11104764

申请日：2005-04-12

Applicant: Donald Canaperi ,  Timothy Dalton ,  Stephen Gates ,  Mahadevaiyer Krishnan ,  Satya Nitta ,  Sampath Purushothaman ,  Sean Smith

Inventor： Donald Canaperi ,  Timothy Dalton ,  Stephen Gates ,  Mahadevaiyer Krishnan ,  Satya Nitta ,  Sampath Purushothaman ,  Sean Smith

IPC: H01L21/768 ,  H01L21/00 ,  H01L21/4763

CPC classification number: H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure incorporates very low dielectric constant (k) insulators with copper wiring to achieve high performance interconnects. The wiring is supported by a relatively durable low k dielectric such as SiLk or SiO2 and a very low k and less-robust gap fill dielectric is disposed in the remainder of the structure, so that the structure combines a durable layer for strength with a very low k dielectric for interconnect electrical performance.

Abstract translation: 一个结构包含非常低的介电常数（k）绝缘体与铜布线，以实现高性能互连。 布线由相对耐用的低k电介质（例如SiLk或SiO 2）支撑，并且在该结构的其余部分中布置非常低的k和较不稳定的间隙填充电介质，使得该结构将耐用层与强度非常相似 低k电介质用于互连电气性能。

公开(公告)号：US20050008959A1

公开(公告)日：2005-01-13

申请号：US10915087

申请日：2004-08-10

Applicant: Stephen Gates ,  Jeffrey Hedrick ,  Elbert Huang ,  Dirk Pfeiffer

Inventor： Stephen Gates ,  Jeffrey Hedrick ,  Elbert Huang ,  Dirk Pfeiffer

IPC: G03G13/06 ,  H01L20060101 ,  H01L21/00 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/44 ,  H01L23/48 ,  H05B6/64

CPC classification number: H01L21/02126 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3125 ,  H01L21/316 ,  Y10S430/146 ,  Y10T428/31663

Abstract: The present invention comprises a method for forming a hardmask including the steps of depositing a polymeric preceramic precursor film atop a substrate; converting the polymeric preceramic precursor film into at least one ceramic layer, where the ceramic layer has a composition of SivNwCxOyHz where 0.1≦v≦0.9, 0≦w≦0.5, 0.05≦x≦0.9, 0≦y≦0.5, 0.05≦z≦0.8 for v+w+x+y+z=1; forming a patterned photoresist atop the ceramic layer; patterning the ceramic layer to expose regions of the underlying substrate, where a remaining region of the underlying substrate is protected by the patterned ceramic layer; and etching the exposed region of the underlying substrate. Another aspect of the present invention is a buried etch stop layer having a composition of SivNwCxOyHz where 0.05

Abstract translation: 本发明包括一种用于形成硬掩模的方法，包括以下步骤：在基底顶上沉积聚合物预陶瓷前体膜; 将聚合物前陶瓷前体膜转化为至少一个陶瓷层，其中陶瓷层具有SivNwCxOyHh的组成，其中0.1≤v≤0.9,0≤w≤0.5,0.05≤x≤0.9,0≤ 对于v + w + x + y + z = 1，y <= 0.5,0.05 <= z <= 0.8; 在陶瓷层顶部形成图案化的光刻胶; 图案化陶瓷层以暴露下面的衬底的区域，其中下面的衬底的剩余区域被图案化的陶瓷层保护; 并蚀刻下面的衬底的暴露区域。 本发明的另一方面是具有SivNwCxOyHz组成的掩埋蚀刻停止层，其中0.05≤v≤0.8,0

公开(公告)号：US20070237970A1

公开(公告)日：2007-10-11

申请号：US11763829

申请日：2007-06-15

Applicant: Stephan Cohen ,  Stephen Gates ,  Alfred Grill ,  Vishnubhai Patel

Inventor： Stephan Cohen ,  Stephen Gates ,  Alfred Grill ,  Vishnubhai Patel

IPC: C23C16/00 ,  B32B9/04

CPC classification number: H01L21/02167 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/12535 ,  Y10T428/24917 ,  Y10T428/249953 ,  H01L2924/00

Abstract: A diffusion barrier useful in semiconductor electronic devices, such as multi-level interconnect wiring structures, is provided. The diffusion barrier is characterized as having a low-dielectric constant of less than 3.5, preferably less than 3.0, as well as being capable of substantially preventing Cu and/or oxygen from diffusing into the active device areas of the electronic device. Since the diffusion barrier has a low-dielectric constant, the diffusion barrier has only a minor effect on the effective dielectric constant of the interconnect structure. The low-k diffusion battier includes atoms of Si, C, H and N. The N atoms are non-uniformly distributed within the low-k diffusion barrier. Optionally, the low-k diffusion barrier may include atoms of Ge, O, halogens such as F or any combination thereof.

Abstract translation: 提供了可用于诸如多层互连布线结构的半导体电子器件中的扩散屏障。 扩散阻挡层的特征在于具有小于3.5，优选小于3.0的低介电常数，并且能够基本上防止Cu和/或氧扩散到电子器件的有源器件区域。 由于扩散阻挡层具有低介电常数，所以扩散阻挡层对互连结构的有效介电常数只有较小的影响。 低k扩散阻挡层包括Si，C，H和N的原子.N原子在低k扩散势垒内不均匀分布。 任选地，低k扩散阻挡层可以包括Ge，O的原子，诸如F的卤素或其任何组合。

公开(公告)号：US20070228570A1

公开(公告)日：2007-10-04

申请号：US11763135

申请日：2007-06-14

Applicant: Christos Dimitrakopoulos ,  Stephen Gates ,  Vincent McGahay ,  Sanjay Mehta

Inventor： Christos Dimitrakopoulos ,  Stephen Gates ,  Vincent McGahay ,  Sanjay Mehta

IPC: H01L23/532

CPC classification number: H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.

Abstract translation: 本发明涉及改进单镶嵌型或双镶嵌型互连结构的制造方法，其中在制造之后金属线之间没有硬掩模保持或导电性问题。 本发明的方法包括化学机械抛光和紫外线曝光或化学修复处理的至少步骤，这些步骤提高了形成的互连结构的可靠性。 本发明还涉及一种互连结构，其包括SiCOH型的多孔超低k电介质，其中其表面层被修饰以形成具有密度梯度和C含量梯度的梯度层。

公开(公告)号：US20070196639A1

公开(公告)日：2007-08-23

申请号：US11190360

申请日：2005-07-27

Applicant: Stephen Gates ,  Alfred Grill ,  Deborah Neumayer ,  Son Nguyen ,  Vishnubhai Patel

Inventor： Stephen Gates ,  Alfred Grill ,  Deborah Neumayer ,  Son Nguyen ,  Vishnubhai Patel

IPC: B32B3/00

CPC classification number: H01B19/04 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10T428/249967 ,  Y10T428/24997 ,  Y10T428/249978 ,  Y10T428/249979 ,  H01L2924/00

Abstract: The present invention provides a porous composite material in which substantially all of the pores within the composite material are small having a diameter of about 5 nm or less and with a narrow PSD. The inventive composite material is also characterized by the substantial absence of the broad distribution of larger sized pores which is prevalent in prior art porous composite materials. The porous composite material includes a first solid phase having a first characteristic dimension and a second solid phase comprised of pores having a second characteristic dimension, wherein the characteristic dimensions of at least one of said phases is controlled to a value of about 5 nm or less.

Abstract translation: 本发明提供一种多孔复合材料，其中复合材料中的基本上所有的孔都具有小直径约5nm或更小并具有窄PSD的孔。 本发明的复合材料的特征还在于现有技术的多孔复合材料中普遍存在的较大尺寸的孔的基本上不存在。 多孔复合材料包括具有第一特征尺寸的第一固相和由具有第二特征尺寸的孔组成的第二固相，其中至少一个所述相的特征尺寸被控制为约5nm或更小的值 。

公开(公告)号：US20060110937A1

公开(公告)日：2006-05-25

申请号：US11324479

申请日：2006-01-03

Applicant: Stephen Gates ,  Alfred Grill ,  David Medeiros ,  Deborah Newmayer ,  Son Nguyen ,  Vishnubhai Patel ,  Xinhui Wang

Inventor： Stephen Gates ,  Alfred Grill ,  David Medeiros ,  Deborah Newmayer ,  Son Nguyen ,  Vishnubhai Patel ,  Xinhui Wang

IPC: H01L21/31

CPC classification number: H01L21/3122 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/31695

Abstract: A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of a thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, silane derivatives, for instance, diethoxymethylsilane (DEMS) and organic molecules, for instance, bicycloheptadiene and cyclopentene oxide.

公开(公告)号：US20060091559A1

公开(公告)日：2006-05-04

申请号：US10981233

申请日：2004-11-04

Applicant: Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

Inventor： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

IPC: H01L21/4763 ,  H01L23/52 ,  H01L21/31

CPC classification number: H01L21/3148 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

Abstract: The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

公开(公告)号：US20050194619A1

公开(公告)日：2005-09-08

申请号：US11040778

申请日：2005-01-21

Applicant: Daniel Edelstein ,  Stephen Gates ,  Alfred Grill ,  Michael Lane ,  Robert Miller ,  Deborah Neumayer ,  Son Nguyen

Inventor： Daniel Edelstein ,  Stephen Gates ,  Alfred Grill ,  Michael Lane ,  Robert Miller ,  Deborah Neumayer ,  Son Nguyen

IPC: H01L27/148 ,  H01L31/103

CPC classification number: H01L31/103 ,  Y10T428/31663

Abstract: A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CH3 functional groups, and another fraction of the C atoms are bonded as Si—R—Si, wherein R is phenyl, —[CH2]n— where n is greater than or equal to 1, HC═CH, C═CH2, C═C or a [S]n linkage, where n is a defined above.

Abstract translation: 提供了一种用于包括互连和感测结构的电子结构中具有增强的内聚强度的低k介电材料，其包括Si，C，O和H的原子，其中C原子的一部分键合为Si-CH _{3个官能团，另外一部分C原子键合为Si-R-Si，其中R是苯基， - [CH 2 N] - 其中n大于或等于1，HC-CH，C-CH 2，CC或[S] N n连接，其中n定义如上。}

公开(公告)号：US20050184397A1

公开(公告)日：2005-08-25

申请号：US10780554

申请日：2004-02-19

Applicant: Stephen Gates ,  Son Nguyen

Inventor： Stephen Gates ,  Son Nguyen

IPC: H01L21/768 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An improved back end of the line (BEOL) interconnect structure comprising an ultralow k (ULK) dielectric is provided. The structure may be of the single or dual damascene type and comprises a dense thin dielectric layer (TDL) between a metal barrier layer and the ULK dielectric. Disclosed are also methods of fabrication of BEOL interconnect structures, including (i) methods in which a dense TDL is provided on etched opening of a ULK dielectric and (ii) methods in which a ULK dielectric is placed in a process chamber on a cold chuck, a sealing agent is added to the process chamber, and an activation step is performed.

Abstract translation: 提供包括超低k（ULK）电介质的线（BEOL）互连结构的改进的后端。 该结构可以是单镶嵌型或双镶嵌型，并且在金属阻挡层和ULK电介质之间包括致密的薄介电层（TDL）。 公开了制造BEOL互连结构的方法，包括（i）其中在ULK电介质的蚀刻开口上提供致密TDL的方法，以及（ii）将ULK电介质放置在冷卡盘上的处理室中的方法 ，在处理室中加入密封剂，进行活化工序。