公开(公告)号：US5973964A

公开(公告)日：1999-10-26

申请号：US182630

申请日：1998-10-30

Applicant: Tsunehiro Tobita ,  Jun Kitahara ,  Takashi Tsunehiro ,  Kunihiro Katayama ,  Ryuichi Hattori ,  Yukihiro Seki ,  Hajime Yamagami ,  Takashi Totsuka ,  Takeshi Wada ,  Yosio Takaya ,  Manabu Saito ,  Kenichi Kaki ,  Takao Okubo ,  Takashi Kikuchi ,  Masamichi Kishi ,  Takeshi Suzuki ,  Shigeru Kadowaki

Inventor： Tsunehiro Tobita ,  Jun Kitahara ,  Takashi Tsunehiro ,  Kunihiro Katayama ,  Ryuichi Hattori ,  Yukihiro Seki ,  Hajime Yamagami ,  Takashi Totsuka ,  Takeshi Wada ,  Yosio Takaya ,  Manabu Saito ,  Kenichi Kaki ,  Takao Okubo ,  Takashi Kikuchi ,  Masamichi Kishi ,  Takeshi Suzuki ,  Shigeru Kadowaki

IPC: G06F3/06 ,  G06F11/14 ,  G06F12/08 ,  G11C29/00 ,  G11C7/00

CPC classification number: G11C29/765 ,  G06F11/1433 ,  G06F11/1441 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0866 ,  G06F3/0601 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/068 ,  G11C29/789 ,  G11C29/82 ,  G06F2003/0694 ,  G06F2212/2022 ,  G06F2212/312

Abstract: A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller has a control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.

公开(公告)号：US5862083A

公开(公告)日：1999-01-19

申请号：US640998

申请日：1996-04-30

Applicant: Tsunehiro Tobita ,  Jun Kitahara ,  Takashi Tsunehiro ,  Kunihiro Katayama ,  Ryuichi Hattori ,  Yukihiro Seki ,  Hajime Yamagami ,  Takashi Totsuka ,  Takeshi Wada ,  Yosio Takaya ,  Manabu Saito ,  Kenichi Kaki ,  Takao Okubo ,  Takashi Kikuchi ,  Masamichi Kishi ,  Takeshi Suzuki ,  Shigeru Kadowaki

Inventor： Tsunehiro Tobita ,  Jun Kitahara ,  Takashi Tsunehiro ,  Kunihiro Katayama ,  Ryuichi Hattori ,  Yukihiro Seki ,  Hajime Yamagami ,  Takashi Totsuka ,  Takeshi Wada ,  Yosio Takaya ,  Manabu Saito ,  Kenichi Kaki ,  Takao Okubo ,  Takashi Kikuchi ,  Masamichi Kishi ,  Takeshi Suzuki ,  Shigeru Kadowaki

IPC: G06F3/06 ,  G06F11/14 ,  G06F12/08 ,  G11C29/00 ,  G11C16/06

CPC classification number: G11C29/765 ,  G06F11/1433 ,  G06F11/1441 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0866 ,  G06F3/0601 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/068 ,  G11C29/789 ,  G11C29/82 ,  G06F2003/0694 ,  G06F2212/2022 ,  G06F2212/312

Abstract: A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.

Abstract translation: 当闪存用作信息处理系统中的半导体盘或主存储器时的控制方法和系统。 半导体文件系统包括电可擦除的第一非易失性存储器，不电可擦除的第二非易失性存储器，易失性存储器，控制存储器的控制器和控制控制器的控制部分，其中对应于由 访问一个外部系统。 第一非易失性存储器存储用于执行操作的外部系统的数据，指示存储数据的物理地址与逻辑地址之间的对应关系的第一管理信息，以及指示第一非易失性存储器的状态的第二管理信息。 第二非易失性存储器预先存储从外部系统输入和输出数据所需的接口信息以及数据的只读数据。 控制器包括控制装置，用于当数据从第一非易失性存储器输出时或当数据被输入到易失性存储器时，确定形成物理地址的预定高位的物理扇区地址，存储确定的物理扇区地址的装置，以及 用于连续地产生由物理扇区地址确定的扇区中的地址的装置。

公开(公告)号：US5287484A

公开(公告)日：1994-02-15

申请号：US976645

申请日：1992-11-13

Applicant: Osamu Nishii ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Takashi Kikuchi ,  Yasuhiko Saigou

Inventor： Osamu Nishii ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Takashi Kikuchi ,  Yasuhiko Saigou

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0897

Abstract: A non-shared system with respect to an outside and an inside cache in a multi-processor system has multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to the transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated in either copy back or write once system. As a result, even though the invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and the outside caches 12, 22, it is extremely improbably for the address of access for writing to conflict with a signal on the bidirectional connection.

Abstract translation: 关于多处理器系统中的外部和内部高速缓存的非共享系统具有多层分层高速缓存。 主存储器地址总线31上的与主存储器30的重写有关的无效地址经由第一和第二路径35,36被发送到高速缓存11,21内部，以使这些内部缓存11,21无效。 无效地址通过主存储器地址总线31和外部高速缓存12,22之间的双向连接被发送到外部高速缓存12,22，以使这些外部高速缓存12,22成为无效。对于写入访问地址是非常不可能的 由于外部高速缓存12,22以一个或多个拷贝的一次系统操作，所以传送到主存储器地址总线31。 结果，即使无效地址经由主存储器地址总线31和外部高速缓存12,22之间的双向连接被发送到外部高速缓存12,22，对于写入冲突的访问地址极其不可能 在双向连接上有一个信号。

公开(公告)号：US5202969A

公开(公告)日：1993-04-13

申请号：US871906

申请日：1992-04-21

Applicant: Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

Inventor： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

IPC: G06F12/08 ,  G11C11/4096

CPC classification number: G06F12/0804 ,  G11C11/4096

Abstract: In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

Abstract translation: 在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。 在缓冲寄存器和数据存储器之间连接一个选择器。 该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。 数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。 这种布置为高速缓冲存储器提供部分写入功能。

公开(公告)号：US5031057A

公开(公告)日：1991-07-09

申请号：US465714

申请日：1990-01-16

Applicant: Takashi Kikuchi ,  Shigeo Aoyagi

Inventor： Takashi Kikuchi ,  Shigeo Aoyagi

IPC: G11B15/68

CPC classification number: G11B15/6815

Abstract: A mechanism in an automatic tape cassette changer for engaging and moving tape cassettes from a tape cassette container to engage a tape cassette player/recorder. The mechanism comprising an engagement mechanism on a rail and a cam mechanism, where the engagement mechanism engages one of a plurality of tape cassettes in a tape cassette container and moves the tape cassette engaged along the rail to a second position where the cam mechanism causes the tape cassette engaged to move into a playing/recording position of a tape cassette player/recorder, the engagement mechanism then moves back along the rail to its initial position and remains there during the playing/recording of the tape cassette engaged with the tape cassette player/recorder. The mechanism provides for this series of steps to be performed in reverse when the tape cassette in the cassette tape player/recorder is to be moved back from the tape cassette player/recorder to the tape cassette container.

Abstract translation: 用于从带盒容器接合和移动带盒以接合带盒播放器/记录器的自动带盒更换器中的机构。 该机构包括在轨道和凸轮机构上的接合机构，其中接合机构接合带盒容器中的多个带盒中的一个，并将沿着轨道接合的带盒移动到第二位置，在该第二位置，凸轮机构引起 盒式磁带被接合以移动到盒式磁带播放器/记录器的播放/记录位置，接合机构然后沿着轨道向后移动到其初始位置，并且在与盒式磁带播放机接合的磁带的播放/记录期间保持在那里 /录音机。 当盒式磁带播放器/记录器中的磁带盒要从磁带播放器/记录器返回到磁带盒容器时，该机构可以反向执行一系列步骤。

公开(公告)号：US5005090A

公开(公告)日：1991-04-02

申请号：US591348

申请日：1990-10-01

Applicant: Takashi Kikuchi ,  Shigeo Aoyagi

Inventor： Takashi Kikuchi ,  Shigeo Aoyagi

IPC: G11B15/68

CPC classification number: G11B15/6815

Abstract: A tape container in an automatic tape cassette changer for holding a plurality of cassette tapes. The tape container having holes in its partition walls corresponding to locations adjacent to the hubs in each cassette tape, such that a hub locking mechanism is capable of passing through the holes to engage the hubs of the cassette tapes disposed in the tape container. The hub locking mechanism is a rod member having a protrusion engagable with a protrusion in the hub of the cassette tapes disposed in the tape container. The rod member has an end portion which is tapered.

公开(公告)号：US4858733A

公开(公告)日：1989-08-22

申请号：US138114

申请日：1987-12-28

Applicant: Takeshi Noguchi ,  Takashi Kikuchi ,  Kazuya Takano

Inventor： Takeshi Noguchi ,  Takashi Kikuchi ,  Kazuya Takano

IPC: F16F9/46 ,  B60G17/015 ,  B60G17/048 ,  B60G17/08 ,  B60N2/52 ,  F16F9/08 ,  F16F9/50 ,  F16F9/53 ,  G12B5/00

CPC classification number: B60N2/505 ,  B60N2/522 ,  B60N2/525 ,  B60N2/527 ,  F16F9/532 ,  G12B5/00

Abstract: A liquid-filled suspension device having an inner cylinder, an outer cylinder, and an elastic member connecting these cylinders to each other. A connecting member is arranged on the cylinder, a closed liquid chamber formed inside at least one of the inner and outer cylinders, a restricted passage formed in the middle portion of the closed liquid chamber, and a flexible membrane member arranged in the closed liquid chamber. An electroviscous liquid is filled in the closed liquid chamber, and two electrode plates arranged in the restricted passage. In this suspension device is used a control device having sensors arranged on these cylinders, and arithmetic decision logic operated by signals from these sensors, and a high-voltage generating circuit operated by signal from the arithmetic decision logic.

Abstract translation: 一种液体填充悬挂装置，其具有内筒，外筒和将这些气缸相互连接的弹性构件。 连接构件设置在气缸上，形成在内筒和外筒中的至少一个内部的封闭液室，形成在密闭液室的中部的限制通道和布置在密闭液室中的柔性膜构件 。 电液体填充在封闭的液体室中，并且两个电极板布置在限制通道中。 在该悬架装置中，使用具有布置在这些气缸上的传感器的控制装置，以及由这些传感器的信号运行的算术判定逻辑，以及由算术判定逻辑信号操作的高电压发生电路。

公开(公告)号：US4320496A

公开(公告)日：1982-03-16

申请号：US890761

申请日：1978-03-27

Applicant: Takashi Kikuchi

Inventor： Takashi Kikuchi

IPC: G11B3/095 ,  G11B3/06 ,  G11B3/085 ,  G11B17/06

CPC classification number: G11B3/08512 ,  G11B3/06

Abstract: A first generator 1 produces a continuously increasing signal corresponding to the tone arm pick-up stylus position, and a second generator 2 produces a synchronizing signal comprising a pulse for each turntable rotation. The synchronizing pulses alternately trigger a pair of parallel sample and hold circuits 4a, 4b supplied with the position signal, whose differential output S is compared with a reference signal T. When the former exceeds the latter the tone arm is returned. Any cyclical variations in the position signal due to the eccentricity of the record spindle hole are self-cancelling during the differential comparison because their magnitudes are substantially the same when sampled during the same relative periods of the turntable rotation cycle. The high pitch of the lead-out groove at the end of the record play produces a large differential output signal, to thereby trigger the tone arm return.In a second embodiment a variable amplitude pulse generator is employed whose turntable revolution synchronized output pulses each have an amplitude corresponding to the instantaneous tone arm position. Such pulses thus serve the dual functions of providing synchronized gating signals and indicating the rotational position of the tone arm.

Abstract translation: 第一发生器1产生对应于色调臂拾取针位置的连续增加的信号，第二发生器2产生包括用于每个转台旋转的脉冲的同步信号。 同步脉冲交替地触发被提供有位置信号的一对并行取样和保持电路4a，4b，其差分输出S与参考信号T相比较。当前者超过后者时，音臂被返回。 在差动比较期间，由于记录主轴孔的偏心引起的位置信号的任何周期性变化都是自消除的，因为当在转盘旋转周期的相同相对周期期间采样时，其幅值基本相同。 记录播放结束时的引出槽的高音高产生大的差分输出信号，从而触发音臂返回。 在第二实施例中，使用可变幅度脉冲发生器，其转盘旋转同步输出脉冲各自具有对应于瞬时音调臂位置的幅度。 因此，这样的脉冲具有提供同步门控信号并指示音调臂的旋转位置的双重功能。

公开(公告)号：US08658885B2

公开(公告)日：2014-02-25

申请号：US12993467

申请日：2009-05-15

Applicant: Takashi Kikuchi ,  Toshiaki Sasaki

Inventor： Takashi Kikuchi ,  Toshiaki Sasaki

IPC: H01L31/00 ,  B05D1/18 ,  B05D3/00

CPC classification number: H01L31/02168 ,  H01L31/03921 ,  H01L31/046 ,  H01L31/0463 ,  H01L31/076 ,  H01L31/1804 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

Abstract: Provided is a substrate for a thin-film photoelectric conversion device which makes it possible to produce the device having improved characteristics at low cost and high productivity. The substrate includes a transparent base member, with a transparent underlying layer and a transparent electrode layer successively stacked on one main surface of the transparent base member. The underlying layer includes transparent insulating fine particles and transparent binder, and the particles are dispersed to cover the one main surface with a coverage factor of particles ranging from 30% or more to less than 80%. An antireflection layer is provided on the other main surface of the transparent base. The antireflection layer includes transparent insulating fine particles and transparent binder, and the particles are dispersed to cover the other main surface with a coverage factor greater than the underlying layer. The transparent electrode layer contains zinc oxide deposited by low-pressure CVD method.

Abstract translation: 本发明提供一种薄膜光电转换装置用基板，能够以低成本，高生产率制造具有改善特性的装置。 基板包括透明基底构件，透明基底层和依次层叠在透明基底构件的一个主表面上的透明电极层。 下层包括透明绝缘细颗粒和透明粘合剂，并且颗粒被分散以覆盖一个主表面，其覆盖因子为30％以上至小于80％。 在透明基材的另一个主表面上设置防反射层。 抗反射层包括透明绝缘细颗粒和透明粘合剂，并且颗粒被分散以覆盖另一个主表面，覆盖因子大于下层。 透明电极层含有通过低压CVD法沉积的氧化锌。

公开(公告)号：US08518744B2

公开(公告)日：2013-08-27

申请号：US13044525

申请日：2011-03-09

Applicant: Takashi Kikuchi ,  Koichi Kanemoto ,  Chuichi Miyazaki ,  Toshihiro Shiotsuki

Inventor： Takashi Kikuchi ,  Koichi Kanemoto ,  Chuichi Miyazaki ,  Toshihiro Shiotsuki

IPC: H01L21/60

CPC classification number: H01L24/83 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/274 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/49113 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/85181 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2224/29099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved.In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.

Abstract translation: 通过经由具有粘合性的绝缘膜积聚的状态，具有存储在同一密封体中平面尺寸不同的多个半导体芯片的结构的半导体器件的可靠性得到改善。 在具有这样的结构的半导体器件中，其结构是在通过DAF积聚的状态下，在相同的密封体中存储有多个平面尺寸不同的半导体芯片的半导体器件，最上半导体芯片的背面的DAF的厚度与 控制电路的形成比形成有存储电路的下层半导体芯片的背面的DAF的厚度大。 因此，可以减少连接最上半导体芯片和布线基板的接合线与下层半导体芯片的主表面角部接触的缺陷。