公开(公告)号：US06831364B2

公开(公告)日：2004-12-14

申请号：US10210173

申请日：2002-08-01

申请人： Timothy Joseph Dalton ,  Stephen Edward Greco ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Kenneth Parker Rodbell ,  Robert Rosenberg

发明人： Timothy Joseph Dalton ,  Stephen Edward Greco ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Kenneth Parker Rodbell ,  Robert Rosenberg

IPC分类号： H01L2352

CPC分类号： H01L21/02126 ,  H01L21/02203 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76828 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus forming a dielectric material that has a low dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.

摘要翻译： 公开了一种在电子结构中形成多孔介电材料层的方法和形成的结构。 在该方法中，半导体器件中的多孔电介质层可以通过首先形成无孔介电层，然后通过反应离子蚀刻进行部分固化，图案化，并且在比无孔介电层更高的温度下最终固化无孔介电层 部分固化温度以将无孔电介质材料转变为多孔电介质材料，从而形成具有低介电常数（即小于2.6）的电介质材料。 无孔介电材料可以通过将热稳定的介电材料如甲基倍半硅氧烷，氢倍半硅氧烷，苯并环丁烯或芳族热固性聚合物与其中的第二相聚合物材料嵌入而形成，使得在较高固化温度下，第二相聚合物材料 基本上挥发以在形成空隙填充的电介质材料之后留下空隙。

公开(公告)号：US06815329B2

公开(公告)日：2004-11-09

申请号：US10117797

申请日：2002-04-02

申请人： Katherina E. Babich ,  Roy Arthur Carruthers ,  Timothy Joseph Dalton ,  Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Ebony Lynn Mays ,  Laurent Perraud ,  Sampath Purushothaman ,  Katherine Lynn Saenger

发明人： Katherina E. Babich ,  Roy Arthur Carruthers ,  Timothy Joseph Dalton ,  Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Ebony Lynn Mays ,  Laurent Perraud ,  Sampath Purushothaman ,  Katherine Lynn Saenger

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/7681 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

摘要翻译： 描述了一种新颖的含气隙的互连布线结构，其在通孔级中结合有固体低k电介质，并且在布线层中结合了复合固体和气隙电介质。 还提供了形成这种互连结构的方法。 该方法很容易扩展到包含多个布线级别的互连结构，并且与双镶嵌后端（BEOL）处理兼容。

公开(公告)号：US06784485B1

公开(公告)日：2004-08-31

申请号：US09502729

申请日：2000-02-11

申请人： Stephan Alan Cohen ,  Timothy Joseph Dalton ,  John Anthony Fitzsimmons ,  Stephen McConnell Gates ,  Lynne M. Gignac ,  Paul Charles Jamison ,  Kang-Wook Lee ,  Sampath Purushothaman ,  Darryl D. Restaino ,  Eva Simonyi ,  Horatio Seymour Wildman

发明人： Stephan Alan Cohen ,  Timothy Joseph Dalton ,  John Anthony Fitzsimmons ,  Stephen McConnell Gates ,  Lynne M. Gignac ,  Paul Charles Jamison ,  Kang-Wook Lee ,  Sampath Purushothaman ,  Darryl D. Restaino ,  Eva Simonyi ,  Horatio Seymour Wildman

IPC分类号： H01L29792

CPC分类号： H01L21/76832 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76834 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device containing a diffusion barrier layer is provided. The semiconductor device includes at least a semiconductor substrate containing conductive metal elements; and, a diffusion barrier layer applied to at least a portion of the substrate in contact with the conductive metal elements, the diffusion barrier layer having an upper surface and a lower surface and a central portion, and being formed from silicon, carbon, nitrogen and hydrogen with the nitrogen being non-uniformly distributed throughout the diffusion barrier layer. Thus, the nitrogen is more concentrated near the lower and upper surfaces of the diffusion barrier layer as compared to the central portion of the diffusion barrier layer. Methods for making the semiconductor devices are also provided.

摘要翻译： 提供了包含扩散阻挡层的半导体器件。 半导体器件至少包括含有导电金属元素的半导体衬底; 以及扩散阻挡层，其被施加到与所述导电金属元件接触的所述基板的至少一部分，所述扩散阻挡层具有上表面，下表面和中心部分，并且由硅，碳，氮和 氢与氮在整个扩散阻挡层中不均匀地分布。 因此，与扩散阻挡层的中心部分相比，氮在扩散阻挡层的下表面和上表面附近更集中。 还提供了制造半导体器件的方法。

公开(公告)号：US06451712B1

公开(公告)日：2002-09-17

申请号：US09739935

申请日：2000-12-18

申请人： Timothy Joseph Dalton ,  Stephen Edward Greco ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Kenneth Parker Rodbell ,  Robert Rosenberg

发明人： Timothy Joseph Dalton ,  Stephen Edward Greco ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Kenneth Parker Rodbell ,  Robert Rosenberg

IPC分类号： H01L2131

CPC分类号： H01L21/02126 ,  H01L21/02203 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76828 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus achieving a dielectric material that has significantly improved dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.

摘要翻译： 公开了一种在电子结构中形成多孔介电材料层的方法和形成的结构。 在该方法中，半导体器件中的多孔电介质层可以通过首先形成无孔介电层，然后通过反应离子蚀刻进行部分固化，图案化，并且在比无孔介电层更高的温度下最终固化无孔介电层 部分固化温度以将无孔电介质材料转化为多孔电介质材料，从而获得具有显着改善介电常数（即小于2.6）的电介质材料。 无孔介电材料可以通过将热稳定的介电材料如甲基倍半硅氧烷，氢倍半硅氧烷，苯并环丁烯或芳族热固性聚合物与其中的第二相聚合物材料嵌入而形成，使得在较高的固化温度下，第二相聚合物材料 基本上挥发以在形成空隙填充的电介质材料之后留下空隙。

公开(公告)号：US08269291B2

公开(公告)日：2012-09-18

申请号：US13007130

申请日：2011-01-14

申请人： Leena Paivikki Buchwalter ,  Kevin Kok Chan ,  Timothy Joseph Dalton ,  Christopher Vincent Jahnes ,  Jennifer Louise Lund ,  Kevin Shawn Petraraca ,  James Louis Speidell ,  James Francis Ziegler

发明人： Leena Paivikki Buchwalter ,  Kevin Kok Chan ,  Timothy Joseph Dalton ,  Christopher Vincent Jahnes ,  Jennifer Louise Lund ,  Kevin Shawn Petraraca ,  James Louis Speidell ,  James Francis Ziegler

IPC分类号： G01L9/00 ,  H01L29/84

CPC分类号： B81C1/00246 ,  B81B2201/0271 ,  B81C1/0023 ,  B81C2203/0735 ,  H03H3/0072 ,  H03H9/2405

摘要： A microelectromechanical system (MEMS) resonator or filter including a first conductive layer, one or more electrodes patterned in the first conductive layer which serve the function of signal input, signal output, or DC biasing, or some combination of these functions, an evacuated cavity, a resonating member comprised of a lower conductive layer and an upper structural layer, a first air gap between the resonating member and one or more of the electrodes, an upper membrane covering the cavity, and a second air gap between the resonating member and the upper membrane.

摘要翻译： 一种微机电系统（MEMS）谐振器或滤波器，其包括第一导电层，在第一导电层中图案化的一个或多个电极，其用于信号输入，信号输出或DC偏置的功能，或这些功能的某些组合;抽真空腔 ，由下导电层和上结构层构成的谐振构件，在谐振构件和一个或多个电极之间的第一气隙，覆盖空腔的上膜，以及谐振构件和第二气隙之间的第二气隙 上膜。

公开(公告)号：US08146046B2

公开(公告)日：2012-03-27

申请号：US12120701

申请日：2008-05-15

申请人： Timothy Joseph Dalton ,  Marc Raymond Faucher ,  Paul David Kartschoke ,  Peter Anthony Sandon

发明人： Timothy Joseph Dalton ,  Marc Raymond Faucher ,  Paul David Kartschoke ,  Peter Anthony Sandon

IPC分类号： G06F17/50

CPC分类号： H01L25/0657 ,  G01R31/31703 ,  G01R31/318513 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure including design data describing a semiconductor structure. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second electric nodes. The second semiconductor chip further includes a first comparing circuit. The semiconductor structure further includes a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip. The first comparing circuit is capable of (i) receiving an input signal from the second electric node directly, (ii) receiving an input signal from the first electric node indirectly through the first coupling via, and (iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different.

摘要翻译： 包括描述半导体结构的设计数据的设计结构。 半导体结构包括第一半导体芯片和第二半导体芯片。 第一半导体芯片位于第二半导体芯片的顶部并结合到第二半导体芯片上。 第一和第二半导体芯片包括第一和第二电节点。 第二半导体芯片还包括第一比较电路。 半导体结构还包括通过将第一半导体芯片的第一电节点电连接到第二半导体芯片的第一比较电路的第一耦合。 第一比较电路能够（i）直接从第二电节点接收输入信号，（ii）通过第一耦合通路间接接收来自第一电节点的输入信号，以及（iii）将第一不匹配信号置于 对来自第一和第二电节点的输入信号的响应是不同的。

公开(公告)号：US20110302542A1

公开(公告)日：2011-12-08

申请号：US13192608

申请日：2011-07-28

申请人： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/481 ,  H01L23/535 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/045 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01007 ,  H01L2924/01022 ,  H01L2924/00

摘要： A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

摘要翻译： 双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线​​水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。

公开(公告)号：US20110241082A1

公开(公告)日：2011-10-06

申请号：US13164173

申请日：2011-06-20

申请人： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

IPC分类号： H01L27/085 ,  H01L23/532

CPC分类号： H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

摘要翻译： 一种半导体结构及其制造方法。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线​​水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。

公开(公告)号：US07923712B2

公开(公告)日：2011-04-12

申请号：US12492618

申请日：2009-06-26

申请人： John Christopher Arnold ,  Lawrence Alfred Clevenger ,  Timothy Joseph Dalton ,  Michael Christopher Gaidis ,  Louis L. Hsu ,  Carl John Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： John Christopher Arnold ,  Lawrence Alfred Clevenger ,  Timothy Joseph Dalton ,  Michael Christopher Gaidis ,  Louis L. Hsu ,  Carl John Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L29/02

CPC分类号： H01L45/1675 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

摘要： A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of the first electrode contacts the phase change element thereby reducing the contact area between the phase change element and the first electrode and thereby increasing the current density through the phase change element and effectively inducing the phase change at lower levels of current and reduced programming power.

摘要翻译： PCM单元结构包括第一电极，相变元件和第二电极，其中相变元件插入在第一电极和第二电极之间，并且仅第一电极的周边边缘与相变元件接触， 减少相变元件与第一电极之间的接触面积，从而增加通过相变元件的电流密度，并有效地在较低的电流电平和降低的编程功率下引起相变。

公开(公告)号：US07473979B2

公开(公告)日：2009-01-06

申请号：US11443394

申请日：2006-05-30

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L29/92

CPC分类号： H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。 在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。 在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。