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    Inverse Quantizer Supporting Multiple Decoding Processes
    23.
    发明申请
    Inverse Quantizer Supporting Multiple Decoding Processes 有权
    逆量化器支持多个解码过程

    公开(公告)号：US20120087593A1

    公开(公告)日：2012-04-12

    申请号：US13079978

    申请日：2011-04-05

    Applicant: Vivian Hsiun ,  Alexander G. MacInnis ,  Xiaodong Xie

    Inventor： Vivian Hsiun ,  Alexander G. MacInnis ,  Xiaodong Xie

    IPC: G06K9/36

    CPC classification number: H04N19/93 ,  H04N5/46 ,  H04N19/105 ,  H04N19/12 ,  H04N19/124 ,  H04N19/126 ,  H04N19/127 ,  H04N19/129 ,  H04N19/136 ,  H04N19/157 ,  H04N19/162 ,  H04N19/176 ,  H04N19/186 ,  H04N19/42 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/82 ,  H04N21/8153

    Abstract: The present invention provides an apparatus for performing inverse quantization for multiple decoding standards, where the functional operations that comprise the inverse quantizer are modularly implemented and can be selectably performed. Each operation can be represented via a table entry in an associated memory area, with the functional operation being performed via reference to that table entry. Functional operations can be bypassed as needed if inverse quantization does not need to be performed on a set of data. Certain other processing operations can be performed between steps as needed to accommodate different coding standards. Macroblock data can be read from and written back to a common storage area, or a direct path is provided for writing the data directly to a subsequent inverse transform device.

    Abstract translation: 本发明提供了一种用于对多个解码标准进行逆量化的装置，其中包括逆量化器的功能操作被模块化地实现并且可以被可选地执行。 可以通过相关联的存储器区域中的表条目来表示每个操作，其中功能操作是通过参考该表项进行的。 如果不需要对一组数据执行逆量化，则可以根据需要绕过功能操作。 可以根据需要在步骤之间执行某些其他处理操作以适应不同的编码标准。 宏块数据可以被读取并写回到公共存储区域，或者提供用于将数据直接写入后续逆变换设备的直接路径。

    VIDEO DECODING SYSTEM SUPPORTING MULTIPLE STANDARDS
    25.
    发明申请
    VIDEO DECODING SYSTEM SUPPORTING MULTIPLE STANDARDS 有权
    视频解码系统支持多种标准

    公开(公告)号：US20110122941A1

    公开(公告)日：2011-05-26

    申请号：US13018840

    申请日：2011-02-01

    Applicant: Alexander G. MacInnis ,  Jose R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

    Inventor： Alexander G. MacInnis ,  Jose R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

    IPC: H04N7/26 ,  H04N7/30

    CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90 ,  H04N19/91

    Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

    Abstract translation: 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反相离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，在给定宏块上执行给定功能的同时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。

    Inverse quantizer supporting multiple decoding processes
    26.
    发明授权
    Inverse quantizer supporting multiple decoding processes 失效
    逆量化器支持多个解码过程

    公开(公告)号：US07920624B2

    公开(公告)日：2011-04-05

    申请号：US10404389

    申请日：2003-04-01

    Applicant: Vivian Hsiun ,  Alexander G. MacInnis ,  Xiaodong Xie

    Inventor： Vivian Hsiun ,  Alexander G. MacInnis ,  Xiaodong Xie

    IPC: H04N7/18

    CPC classification number: H04N19/93 ,  H04N5/46 ,  H04N19/105 ,  H04N19/12 ,  H04N19/124 ,  H04N19/126 ,  H04N19/127 ,  H04N19/129 ,  H04N19/136 ,  H04N19/157 ,  H04N19/162 ,  H04N19/176 ,  H04N19/186 ,  H04N19/42 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/82 ,  H04N21/8153

    Abstract: The present invention provides an apparatus for performing inverse quantization for multiple decoding standards, where the functional operations that comprise the inverse quantizer are modularly implemented and can be selectably performed. Each operation can be represented via a table entry in an associated memory area, with the functional operation being performed via reference to that table entry. Functional operations can be bypassed as needed if inverse quantization does not need to be performed on a set of data. Certain other processing operations can be performed between steps as needed to accommodate different coding standards. Macroblock data can be read from and written back to a common storage area, or a direct path is provided for writing the data directly to a subsequent inverse transform device.

    Abstract translation: 本发明提供了一种用于对多个解码标准进行逆量化的装置，其中包括逆量化器的功能操作被模块化地实现并且可以被可选地执行。 可以通过相关联的存储器区域中的表条目来表示每个操作，其中功能操作是通过参考该表项进行的。 如果不需要对一组数据执行逆量化，则可以根据需要绕过功能操作。 可以根据需要在步骤之间执行某些其他处理操作以适应不同的编码标准。 宏块数据可以被读取并写回到公共存储区域，或者提供用于将数据直接写入后续逆变换设备的直接路径。

    INVERSE DISCRETE COSINE TRANSFORM SUPPORTING MULTIPLE DECODING PROCESSES
    27.
    发明申请
    INVERSE DISCRETE COSINE TRANSFORM SUPPORTING MULTIPLE DECODING PROCESSES 有权
    反向离散COSE变换支持多重解码过程

    公开(公告)号：US20060280374A1

    公开(公告)日：2006-12-14

    申请号：US11466328

    申请日：2006-08-22

    Applicant: Vivian Hsiun ,  Alexander MacInnis ,  Xiaodong Xie ,  Sheng Zhong

    Inventor： Vivian Hsiun ,  Alexander MacInnis ,  Xiaodong Xie ,  Sheng Zhong

    IPC: G06K9/36

    CPC classification number: H04N19/90 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/91

    Abstract: The present invention provides an apparatus and method for providing a programmable inverse discrete cosine transform, wherein the transform coefficients are loaded into a memory area of a core transform device and a variety of coding standards can thereby be handled by the same programmable core device. The core device is configured to process a certain sized data block, and the incoming source blocks are converted to conform to this size. After transformation, the proper sized result can be extracted from the transform device output. A switchable speed-up mode provides for 4-point transforms, rather than 8-point transforms. Alternatively, the invention also provides for dedicated transform hardware to be switchably used in conjunction with programmable transform hardware, depending upon the type of coding being used, and the speed of inverse transform desired.

    Abstract translation: 本发明提供了一种用于提供可编程逆离散余弦变换的装置和方法，其中变换系数被加载到核心变换设备的存储区域中，并且各种编码标准由此可由相同的可编程核心设备处理。 核心设备被配置为处理某个大小的数据块，并且将输入的源块转换为符合该大小。 转换后，可以从变换设备输出中提取适当大小的结果。 可切换的加速模式提供4点变换，而不是8点变换。 或者，本发明还提供了根据所使用的编码类型以及期望的逆变换速度，可编程变换硬件可切换地使用的专用变换硬件。

    Method of communicating between modules in a decoding system
    29.
    发明授权
    Method of communicating between modules in a decoding system 有权
    在解码系统中的模块之间进行通信的方法

    公开(公告)号：US06963613B2

    公开(公告)日：2005-11-08

    申请号：US10114797

    申请日：2002-04-01

    Applicant: Alexander G. MacInnis ,  Vivian Hsiun ,  Sheng Zhong ,  Xiaodong Xie ,  Kimming So ,  Jose′ R. Alvarez

    Inventor： Alexander G. MacInnis ,  Vivian Hsiun ,  Sheng Zhong ,  Xiaodong Xie ,  Kimming So ,  Jose′ R. Alvarez

    IPC: G06F9/38 ,  G06T9/00 ,  H04N7/26 ,  H04N7/30 ,  H04N7/50 ,  H04N7/12

    CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/13 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90

    Abstract: Means of communicating between modules in a decoding system. A variable-length decoding accelerator communicates with a core decoder processor via a co-processor interface. In one embodiment, other decoding accelerators, in addition to the variable-length decoder, are adapted to provide status data indicative of their status to a co-processor status register. In another embodiment, a decoding accelerator is controlled by providing commands to the accelerator via posted write operations and polling the accelerator to determine whether the command has been performed. In still another embodiment, a first hardware accelerator communicates with a core decoder processor via a co-processor interface and other decoding accelerators, in addition to the first hardware accelerator, are adapted to provide status data indicative of their status to a co-processor status register.

    Abstract translation: 在解码系统中的模块之间进行通信的手段。 可变长度解码加速器经由协处理器接口与核心解码器处理器进行通信。 在一个实施例中，除了可变长度解码器之外，其他解码加速器适于向协处理器状态寄存器提供表示其状态的状态数据。 在另一个实施例中，解码加速器通过经由发布的写入操作向加速器提供命令并轮询加速器来控制，以确定该命令是否已被执行。 在另一个实施例中，第一硬件加速器经由协处理器接口与核心解码器处理器进行通信，并且除了第一硬件加速器之外，其他解码加速器适于将表示其状态的状态数据提供给协处理器状态 寄存器。

    Programmable variable-length decoder
    30.
    发明申请
    Programmable variable-length decoder 失效
    可编程可变长度解码器

    公开(公告)号：US20050007264A1

    公开(公告)日：2005-01-13

    申请号：US10911152

    申请日：2004-08-03

    Applicant: Vivian Hsiun

    Inventor： Vivian Hsiun

    IPC: G09G5/06 ,  G09G5/12 ,  G09G5/14 ,  G09G5/28 ,  G09G5/34 ,  G09G5/36 ,  H04N7/26 ,  H04N7/30 ,  H04N7/50 ,  H04N9/64 ,  H03M7/40

    CPC classification number: G09G5/36 ,  G09G5/06 ,  G09G5/12 ,  G09G5/14 ,  G09G5/28 ,  G09G5/346 ,  G09G2310/0224 ,  G09G2340/0407 ,  G09G2340/10 ,  G09G2340/125 ,  G09G2360/125 ,  H04N9/641 ,  H04N19/12 ,  H04N19/122 ,  H04N19/126 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70

    Abstract: System and method for decoding variable-length codes. A variable-length decoder includes an address generator and a local memory unit. The local memory stores a variable-length code look-up table. The local memory can be programmed to include a look-up table supporting substantially any decoding algorithm. In one embodiment, a decoder memory unit and a system memory unit are employed together with the local memory to store a codeword look-up table. The shortest codes are stored in local memory, the next shortest in decoder memory, and the longest codes are stored in system memory. A multistage search algorithm is employed to search for the longest codes. The address generator generates the address of the code table to be searched by adding the value of the bits to be searched to a base address.

    Abstract translation: 用于解码可变长度代码的系统和方法。 可变长度解码器包括地址发生器和本地存储器单元。 本地存储器存储可变长度的代码查找表。 可以将本地存储器编程为包括支持基本上任何解码算法的查找表。 在一个实施例中，解码器存储器单元和系统存储器单元与本地存储器一起被采用以存储码字查找表。 最短的代码存储在本地存储器中，在解码器存储器中是最短的，并且最长的代码存储在系统存储器中。 采用多级搜索算法来搜索最长码。 地址生成器通过将要搜索的位的值添加到基址来生成要搜索的代码表的地址。

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