公开(公告)号：US20160293764A1

公开(公告)日：2016-10-06

申请号：US15073245

申请日：2016-03-17

Applicant: Applied Materials, Inc.

Inventor： Keun-Yong BAN ,  Zhiyuan YE ,  Errol Antonio C. SANCHEZ ,  Xinyu BAO ,  David K. CARLSON

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/205 ,  H01L21/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L29/7849 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02439 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66522

Abstract: Embodiments of the present disclosure generally relate to a semiconductor device including layers of group III-V semiconductor materials. In one embodiment, the semiconductor device includes a phosphorous containing layer deposited on a silicon substrate, wherein a lattice mismatch between the phosphorous containing layer and the silicon substrate is less than 5%, a group III-V compound nucleation layer deposited on the phosphorous containing layer at a first temperature, the group III-V compound nucleation layer having a first thickness, a group III-V compound transition layer deposited on the group III-V compound nucleation layer at a second temperature higher than the first temperature, the group III-V compound transition layer having a second thickness larger than the first thickness, and the group III-V compound nucleation layer is different from the group III-V compound transition layer, and an active layer deposited on the group III-V compound transition layer.

Abstract translation: 本公开的实施例一般涉及包括III-V族III族半导体材料层的半导体器件。 在一个实施例中，半导体器件包括沉积在硅衬底上的含磷层，其中含磷层和硅衬底之间的晶格失配小于5％，III-V族化合物成核层沉积在含磷 III族化合物成核层，第III-V族化合物成核层，第III-V族化合物成核层，第III-V族化合物成核层，第III-V族化合物成核层， -V化合物过渡层，其具有大于第一厚度的第二厚度，III-V族化合物成核层与III-V族化合物过渡层不同，并且沉积在III-V族化合物过渡层上的活性层 。

公开(公告)号：US20160141175A1

公开(公告)日：2016-05-19

申请号：US14540104

申请日：2014-11-13

Applicant: Applied Materials, Inc.

Inventor： Chun YAN ,  Xinyu BAO

IPC: H01L21/02 ,  B08B7/04 ,  B08B5/00 ,  B08B7/00

CPC classification number: H01L21/02661 ,  B08B5/00 ,  B08B7/0035 ,  B08B7/0071 ,  B08B7/04 ,  H01L21/02046 ,  H01L21/0206 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/67115

Abstract: Native oxides and residue are removed from surfaces of a substrate by performing a multiple-stage native oxide cleaning process. In one example, the method for removing native oxides from a substrate includes supplying a first gas mixture including an inert gas onto a surface of a material layer disposed on a substrate into a first processing chamber, wherein the material layer is a III-V group containing layer for a first period of time, supplying a second gas mixture including an inert gas and a hydrogen containing gas onto the surface of the material layer for a second period of time, and supplying a third gas mixture including a hydrogen containing gas to the surface of the material layer while maintaining the substrate at a temperature less than 550 degrees Celsius.

Abstract translation: 通过进行多级自然氧化物清洗工艺，从基底的表面除去天然氧化物和残余物。 在一个实例中，用于从衬底去除天然氧化物的方法包括将包含惰性气体的第一气体混合物供应到设置在衬底上的材料层的表面上的第一处理室中，其中材料层为III-V族 将含有惰性气体和含氢气体的第二气体混合物供给到所述材料层的表面上第二时间段，并将含有含氢气体的第三气体混合物供给到所述第二气体混合物 同时将基板保持在低于550摄氏度的温度。

公开(公告)号：US20150372097A1

公开(公告)日：2015-12-24

申请号：US14313086

申请日：2014-06-24

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Errol Antonio C. SANCHEZ

IPC: H01L29/205 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/0607 ,  B82Y10/00 ,  H01L21/02546 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0673 ,  H01L29/0688 ,  H01L29/1033 ,  H01L29/12 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Embodiments of the present disclosure relate to semiconductor devices such as transistors used for amplifying or switching electronic signals. In one embodiment, a first trench is formed in a dielectric layer formed on a substrate to expose a surface of the substrate, a multi-stack layer structure is formed within the first trench, and a third semiconductor compound layer is formed on the second semiconductor compound layer, wherein the second semiconductor compound layer has an etching resistance against an etchant lower than that of the first and third semiconductor compound layers, a second trench is formed in the dielectric layer to partially expose at least the second semiconductor compound layer and the third semiconductor compound layer, and the second semiconductor compound layer is selectively removed so that the first semiconductor compound layer is isolated from the third semiconductor compound layer by an air gap.

Abstract translation: 本公开的实施例涉及半导体器件，例如用于放大或切换电子信号的晶体管。 在一个实施例中，在形成在基板上的电介质层中形成第一沟槽以暴露衬底的表面，在第一沟槽内形成多层叠层结构，在第二半导体上形成第三半导体化合物层 化合物层，其中所述第二半导体化合物层对于蚀刻剂具有比所述第一和第三半导体化合物层低的蚀刻剂的耐蚀刻性，在所述电介质层中形成第二沟槽，以至少部分地暴露所述第二半导体化合物层和所述第三半导体化合物层 半导体化合物层，并且第二半导体化合物层被选择性地去除，使得第一半导体化合物层通过气隙与第三半导体化合物层隔离。

公开(公告)号：US20200035525A1

公开(公告)日：2020-01-30

申请号：US16591354

申请日：2019-10-02

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/67 ,  H01J37/32 ,  B08B7/00 ,  C30B25/04 ,  C30B25/18 ,  C30B29/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3065 ,  H01L29/66

Abstract: Implementations of the present disclosure generally relate to methods and apparatuses for epitaxial deposition on substrate surfaces. More particularly, implementations of the present disclosure generally relate to an integrated system for processing N-type metal-oxide semiconductor (NMOS) devices. In one implementation, a cluster tool for processing a substrate is provided. The cluster tool includes a pre-clean chamber, an etch chamber, one or more pass through chambers, one or more outgassing chambers, a first transfer chamber, a second transfer chamber, and one or more process chambers. The pre-clean chamber and the etch chamber are coupled to a first transfer chamber. The one or more pass through chambers are coupled to and disposed between the first transfer chamber and the second transfer chamber. The one or more outgassing chambers are coupled to the second transfer chamber. The one or more process chambers are coupled to the second transfer chamber.

公开(公告)号：US20180286961A1

公开(公告)日：2018-10-04

申请号：US15896983

申请日：2018-02-14

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Zhiyuan YE ,  Flora Fong-Song CHANG ,  Abhishek DUBE ,  Xuebin LI ,  Errol Antonio C. SANCHEZ ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/167 ,  H01L29/08

CPC classification number: H01L29/6659 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/41775 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7851

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

公开(公告)号：US20180211881A1

公开(公告)日：2018-07-26

申请号：US15811188

申请日：2017-11-13

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Schubert S. CHU ,  Xinyu BAO ,  Regina Germanie FREED ,  Hua CHUNG

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848 ,  H01L29/7851

Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. In one embodiment, a method for forming a FinFET device includes removing a portion of each fin of a plurality of fins, and a remaining portion of each fin is recessed from a dielectric surface. The method further includes forming a feature on the remaining portion of each fin, filling gaps formed between adjacent features with a dielectric material, removing the features, and forming a fill material on the remaining portion of each fin. Because the shape of the features is controlled, the shape of the fill material can be controlled.

公开(公告)号：US20180082836A1

公开(公告)日：2018-03-22

申请号：US15417496

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Chun YAN ,  Xinyu BAO ,  Melitta Manyin HON ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L21/02057 ,  H01L29/66636 ,  H01L29/66795

Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.

公开(公告)号：US20180082835A1

公开(公告)日：2018-03-22

申请号：US15417466

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Chun YAN ,  Xinyu BAO ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/02 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/67 ,  B08B7/00

CPC classification number: H01L21/02046 ,  B08B7/0035 ,  B08B7/0057 ,  C23C16/4401 ,  C23C16/56 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02664 ,  H01L21/2686 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/67017 ,  H01L21/67034 ,  H01L21/67069 ,  H01L21/67115

Abstract: Implementations disclosed herein relate to methods for controlling substrate outgassing of hazardous gasses after an epitaxial process. In one implementation, the method includes providing a substrate comprising an epitaxial layer into a transfer chamber, wherein the transfer chamber has an ultraviolet (UV) lamp module disposed adjacent to a top ceiling of the transfer chamber, flowing an oxygen-containing gas into the transfer chamber through a gas line of the transfer chamber, flowing a non-reactive gas into the transfer chamber through the gas line of the transfer chamber, activating the UV lamp module to oxidize residues or species on a surface of the substrate to form an outgassing barrier layer on the surface of the substrate, ceasing the flow of the oxygen-containing gas and the nitrogen-containing gas into the transfer chamber, pumping the transfer chamber, and deactivating the UV lamp module.

公开(公告)号：US20180076031A1

公开(公告)日：2018-03-15

申请号：US15418190

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Chun YAN ,  Xinyu BAO ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L21/02664 ,  C23C14/021 ,  C23C14/022 ,  C23C14/5826 ,  C23C14/5873 ,  C23C16/0245 ,  C23C16/24 ,  C23C16/56 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02293 ,  H01L21/02315 ,  H01L21/0234 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02661 ,  H01L21/2018 ,  H01L21/2033 ,  H01L21/76855 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/785

Abstract: Implementations disclosed herein relate to methods for controlling substrate outgassing. In one implementation, the method includes removing oxides from an exposed surface of a substrate in an inductively coupled plasma chamber, forming an epitaxial layer on the exposed surface of the substrate in an epitaxial deposition chamber, and performing an outgassing control of the substrate by subjecting the substrate to a first plasma formed from a first etch precursor in the inductively coupled plasma chamber at a first chamber pressure, wherein the first etch precursor comprises a hydrogen-containing precursor, a chlorine-containing precursor, and an inert gas, and subjecting the substrate to a second plasma formed from a second etch precursor in the inductively coupled plasma chamber at a second chamber pressure that is higher than the first chamber pressure, wherein the second etch precursor comprises a hydrogen-containing precursor and an inert gas.

公开(公告)号：US20170335444A1

公开(公告)日：2017-11-23

申请号：US15668026

申请日：2017-08-03

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan YE ,  Errol Antonio C. SANCHEZ ,  Keun-Yong BAN ,  Xinyu BAO

IPC: C23C8/02 ,  H01L21/02

CPC classification number: C23C8/02 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.