公开(公告)号：US20170255397A1

公开(公告)日：2017-09-07

申请号：US15063186

申请日：2016-03-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Dong Ping Zhang ,  Paula Aguilera Diez

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F3/0613 ,  G06F3/0658 ,  G06F3/0673 ,  G06F12/084 ,  G06F12/0888 ,  G06F12/10 ,  G06F2212/1024

Abstract: Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory where the atomic queue is allocated.

公开(公告)号：US09489321B2

公开(公告)日：2016-11-08

申请号：US13917033

申请日：2013-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： James M. O'Connor ,  Niladrish Chatterjee ,  Nuwan S. Jayasena ,  Gabriel H. Loh

IPC: G06F13/16

CPC classification number: G06F13/1626 ,  G06F13/161 ,  G06F13/1694

Abstract: A memory accessing agent includes a memory access generating circuit and a memory controller. The memory access generating circuit is adapted to generate multiple memory accesses in a first ordered arrangement. The memory controller is coupled to the memory access generating circuit and has an output port, for providing the multiple memory accesses to the output port in a second ordered arrangement based on the memory accesses and characteristics of an external memory. The memory controller determines the second ordered arrangement by calculating an efficient row burst value and interrupting multiple row-hit requests to schedule a row-miss request based on the efficient row burst value.

Abstract translation: 存储器访问代理包括存储器访问生成电路和存储器控制器。 存储器访问生成电路适于以第一有序布置生成多个存储器访问。 存储器控制器耦合到存储器存取产生电路，并且具有输出端口，用于基于存储器访问和外部存储器的特性以第二有序布置提供对输出端口的多个存储器访问。 存储器控制器通过计算有效的行脉冲串值和中断多个行命中请求来基于有效的行脉冲串值来调度行错请求来确定第二排序。

公开(公告)号：US09442557B2

公开(公告)日：2016-09-13

申请号：US14075645

申请日：2013-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Nuwan S. Jayasena ,  Yasuko Eckert ,  Madhu Saravana Sibi Govindan ,  William L. Bircher ,  Michael J. Schulte ,  Srilatha Manne

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3234 ,  G06F1/206

Abstract: The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.

Abstract translation: 所描述的实施例包括具有一个或多个实体（处理器核心，处理器等）的计算设备。 在一些实施例中，在操作期间，计算设备中的热功率管理单元使用线性预测来基于实体的一个或多个先前空闲周期的持续时间来计算实体的下一个空闲周期的预测持续时间。 基于下一个空闲周期的预测持续时间，热功率管理单元将实体配置为在相应的空闲状态下工作。

公开(公告)号：US09344091B2

公开(公告)日：2016-05-17

申请号：US14551147

申请日：2014-11-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Michael J. Schulte ,  Gabriel H. Loh ,  Michael Ignatowski

IPC: H03K19/177 ,  G11C7/00 ,  G06F15/78 ,  G06F13/16 ,  G06F11/10 ,  G06F13/42 ,  G11C7/10 ,  G11C29/00

CPC classification number: H03K19/1776 ,  G06F11/1004 ,  G06F13/1668 ,  G06F13/4234 ,  G06F15/7867 ,  G11C7/1006 ,  G11C7/1048 ,  G11C29/70 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H03K19/17776 ,  Y02D10/14 ,  Y02D10/151

Abstract: A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations and other memory operations that use data stored in the die-stacked memory device or that result in data that is to be stored in the die-stacked memory device. One or more configuration files representing corresponding logic configurations for the reconfigurable logic device can be stored in a configuration store at the die-stacked memory device, and a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. Due to the integration of the logic dies and the memory dies, the reconfigurable logic device can perform various data manipulation operations with higher bandwidth and lower latency and power consumption compared to devices external to the die-stacked memory device.

Abstract translation: 芯片堆叠的存储器件包括可重构逻辑器件，以在执行各种数据操作操作和使用存储在管芯堆叠的存储器件中的数据的其他存储器操作中提供实现灵活性，或者导致要存储在管芯堆叠存储器件中的数据。 堆叠式存储设备。 代表可重配置逻辑器件的相应逻辑配置的一个或多个配置文件可被存储在管芯堆叠的存储器件的配置存储器中，并且配置控制器可使用所选择的一个存储器件对可重新配置的逻辑器件进行编程 配置文件。 由于逻辑管芯和存储器管芯的集成，与可堆叠存储器件外部的器件相比，可重构逻辑器件可以执行具有更高带宽和更低延迟和功耗的各种数据操作操作。

公开(公告)号：US20160048327A1

公开(公告)日：2016-02-18

申请号：US14459958

申请日：2014-08-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Lisa R. Hsu ,  James M. O'Connor

IPC: G06F3/06

CPC classification number: G06F13/1657 ,  G06F13/1647

Abstract: A system and method are disclosed for managing memory interleaving patterns in a system with multiple memory devices. The system includes a processor configured to access multiple memory devices. The method includes receiving a first plurality of data blocks, and then storing the first plurality of data blocks using an interleaving pattern in which successive blocks of the first plurality of data blocks are stored in each of the memory devices. The method also includes receiving a second plurality of data blocks, and then storing successive blocks of the second plurality of data blocks in a first memory device of the multiple memory devices.

Abstract translation: 公开了一种用于管理具有多个存储器件的系统中的存储器交错模式的系统和方法。 该系统包括被配置为访问多个存储器设备的处理器。 该方法包括：接收第一多个数据块，然后使用交织模式存储第一多个数据块，其中第一多个数据块的连续块存储在每个存储器件中。 该方法还包括接收第二多个数据块，然后将第二多个数据块的连续块存储在多个存储器件的第一存储器件中。

公开(公告)号：US09218204B2

公开(公告)日：2015-12-22

申请号：US13725724

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： James M. O'Connor ,  Michael J. Schulte ,  Nuwan S. Jayasena ,  Gabriel H. Loh

IPC: G06F9/50 ,  G06F9/52

CPC classification number: G06F9/50 ,  G06F9/526 ,  G06F2209/521 ,  G06F2209/522

Abstract: A system includes an atomic processing engine (APE) coupled to an interconnect. The interconnect is to couple to one or more processor cores. The APE receives a plurality of commands from the one or more processor cores through the interconnect. In response to a first command, the APE performs a first plurality of operations associated with the first command. The first plurality of operations references multiple memory locations, at least one of which is shared between two or more threads executed by the one or more processor cores.

Abstract translation: 系统包括耦合到互连的原子处理引擎（APE）。 互连将耦合到一个或多个处理器内核。 APE通过互连从一个或多个处理器核接收多个命令。 响应于第一命令，APE执行与第一命令相关联的第一多个操作。 第一组多个操作引用多个存储器位置，其中至少一个在一个或多个处理器核心执行的两个或多个线程之间共享。

公开(公告)号：US20150185801A1

公开(公告)日：2015-07-02

申请号：US14146591

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan S. Jayasena ,  Srilatha Manne ,  Madhu Saravana Sibi Govindan ,  William L. Bircher

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3225 ,  Y02D10/171 ,  Y02D50/20

Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.

Abstract translation: 电源选通决定可以基于缓存污垢的测量。 分析器逻辑可以基于与组件相关联的一个或多个高速缓存的高速缓存污垢来选择性地加电处理系统的组件。 当高速缓存污物超过阈值时，分析器逻辑可以对组件供电，并且当高速缓存污垢不超过阈值时，分析器逻辑可以维持组件处于空闲状态。 空闲时间预测逻辑可以用于预测组件的空闲时间的持续时间。 然后，分析器逻辑可以基于高速缓存污物和预测的空闲时间选择性地对组件进行加电。

公开(公告)号：US20150106574A1

公开(公告)日：2015-04-16

申请号：US14053957

申请日：2013-10-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Anton Chernoff

IPC: G06F3/06

CPC classification number: G06F15/7821 ,  G06F9/3881 ,  G06F2003/0697 ,  Y02D10/12 ,  Y02D10/13

Abstract: The described embodiments include a computing device that comprises at least one memory die having memory circuits and memory die processing circuits, and a logic die coupled to the at least one memory die, the logic die having logic die processing circuits. In the described embodiments, the memory die processing circuits are configured to perform memory die processing operations on data retrieved from or destined for the memory circuits and the logic die processing circuits are configured to perform logic die processing operations on data retrieved from or destined for the memory circuits.

Abstract translation: 所描述的实施例包括计算设备，其包括具有存储器电路和存储器管芯处理电路的至少一个存储器管芯，以及耦合到至少一个存储器管芯的逻辑管芯，所述逻辑管芯具有逻辑管芯处理电路。 在所描述的实施例中，存储器管芯处理电路被配置为对从存储器电路检索或去往存储器电路的数据执行存储器管芯处理操作，并且逻辑管芯处理电路被配置为对从或从 存储电路。

公开(公告)号：US20140149772A1

公开(公告)日：2014-05-29

申请号：US14075645

申请日：2013-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Nuwan S. Jayasena ,  Yasuko Eckert ,  Madhu Saravana Sibi Govindan ,  William L. Bircher ,  Michael J. Schulte ,  Srilatha Manne

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/206

Abstract: The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.

Abstract translation: 所描述的实施例包括具有一个或多个实体（处理器核心，处理器等）的计算设备。 在一些实施例中，在操作期间，计算设备中的热功率管理单元使用线性预测来基于实体的一个或多个先前空闲周期的持续时间来计算实体的下一个空闲周期的预测持续时间。 基于下一个空闲周期的预测持续时间，热功率管理单元将实体配置为在相应的空闲状态下工作。

公开(公告)号：US20240330198A1

公开(公告)日：2024-10-03

申请号：US18192874

申请日：2023-03-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena

IPC: G06F12/1009 ,  G06F12/0837

CPC classification number: G06F12/1009 ,  G06F12/0837

Abstract: Modifying memory page attributes using a programmable page attribute register of a core executing a process is described. In accordance with the described techniques, a host includes a core that is configured to generate a modified page table attribute for a page in system memory. The modified page table attribute represents at least one demoted permission for a page as specified by a system page table. The core is configured to maintain the modified page table attribute locally in the programmable page attribute register and execute at least one operation allocated to the page according to the modified page table attribute.