公开(公告)号：US07211516B2

公开(公告)日：2007-05-01

申请号：US11096660

申请日：2005-04-01

Applicant: Peijun J. Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue Crank ,  Thomas D. Bonifield ,  Homi Mogul

Inventor： Peijun J. Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue Crank ,  Thomas D. Bonifield ,  Homi Mogul

IPC: H01L21/44

CPC classification number: H01L21/28518 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.

公开(公告)号：US20060163651A1

公开(公告)日：2006-07-27

申请号：US11042415

申请日：2005-01-25

Applicant: Antonio Rotondaro ,  Kaiping Liu ,  Jihong Chen ,  Amitabh Jain

Inventor： Antonio Rotondaro ,  Kaiping Liu ,  Jihong Chen ,  Amitabh Jain

IPC: H01L29/06

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/823814 ,  H01L21/823871

Abstract: The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.

Abstract translation: 本发明提供了晶体管器件的制造方法，集成电路的制造方法以及晶体管器件。 制造晶体管器件的方法以及其它步骤包括在衬底上形成栅极结构，并在栅极结构附近形成衬底中的源极/漏极区域，源极/漏极区域具有与衬底形成电连接的边界 。 该方法还包括在衬底中形成位错环，位错环不延伸到源/漏区的边界之外。

公开(公告)号：US20060073656A1

公开(公告)日：2006-04-06

申请号：US10959674

申请日：2004-10-04

Applicant: Amitabh Jain ,  Peijun Chen ,  Jorge Kittl

Inventor： Amitabh Jain ,  Peijun Chen ,  Jorge Kittl

IPC: H01L21/8238 ,  H01L21/44

CPC classification number: H01L21/28518 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/78

Abstract: According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.

公开(公告)号：US20050189660A1

公开(公告)日：2005-09-01

申请号：US10858644

申请日：2004-06-02

Applicant: Haowen Bu ,  Amitabh Jain ,  Wayne Bather ,  Stephanie Butler

Inventor： Haowen Bu ,  Amitabh Jain ,  Wayne Bather ,  Stephanie Butler

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L21/338

CPC classification number: H01L29/6659 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.

Abstract translation: 形成半导体器件的方法包括在栅叠层的外表面上形成一个或多个侧壁间隔层。 至少部分形成的半导体器件的至少一个区域被掺杂。 第一和第二侧壁体形成在栅极堆叠的相对侧上。 第一和第二侧壁体的形成包括在栅极堆叠的外表面和侧壁间隔层上形成第一侧壁形成层，将半导体器件暴露于单个晶片反应器中的加热循环，以及形成第二侧壁 在第一侧壁形成层的外表面上形成层。 第二侧壁形成层的形成发生在基本上最小化部分形成的半导体器件的至少一个区域中的掺杂剂损失和失活的环境中。

公开(公告)号：US20050040496A1

公开(公告)日：2005-02-24

申请号：US10920023

申请日：2004-08-17

Applicant: Amitabh Jain

Inventor： Amitabh Jain

IPC: H01J37/08 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L31/0288

CPC classification number: H01J37/08 ,  H01J2237/31701 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides, for use in a semiconductor manufacturing process, a method (100) of preparing an ion-implantation source material. The method includes providing (110) a deliquescent ion implantation source material and mixing (110) the deliquescent ion implantation source material with an organic liquid to form a paste.

Abstract translation: 为了在半导体制造工艺中使用本发明，提供了制备离子注入源材料的方法（100）。 该方法包括提供（110）潮解离子注入源材料，并将潮解离子注入源材料与有机液体混合（110）以形成糊状物。

公开(公告)号：US06847089B2

公开(公告)日：2005-01-25

申请号：US10407128

申请日：2003-04-03

Applicant: Srinivasan Chakravarthi ,  Suresh Potla ,  Gordon P. Pollack ,  Amitabh Jain

Inventor： Srinivasan Chakravarthi ,  Suresh Potla ,  Gordon P. Pollack ,  Amitabh Jain

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6656

Abstract: An embodiment of the invention is an integrated circuit 2 having halo atoms 12 concentrated at a gate side of a channel region and impurity atoms 14 within the channel region. Another embodiment of the invention is a method of manufacturing an integrated circuit that includes the implantation of impurity atoms 14 into a semiconductor substrate 11.

Abstract translation: 本发明的一个实施例是集成电路2，其具有集中在沟道区的栅极侧的光子原子12和沟道区内的杂质原子14。 本发明的另一实施例是一种制造集成电路的方法，该集成电路包括将杂质原子14注入到半导体衬底11中。

公开(公告)号：US06812073B2

公开(公告)日：2004-11-02

申请号：US10316468

申请日：2002-12-10

Applicant: Haowen Bu ,  Amitabh Jain ,  Wayne A. Bather ,  Stephanie Watts Butler

Inventor： Haowen Bu ,  Amitabh Jain ,  Wayne A. Bather ,  Stephanie Watts Butler

IPC: H01L2100

CPC classification number: H01L29/6659 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.

Abstract translation: 形成半导体器件的方法包括在栅叠层的外表面上形成一个或多个侧壁间隔层。 至少部分形成的半导体器件的至少一个区域被掺杂。 第一和第二侧壁体形成在栅极堆叠的相对侧上。 第一和第二侧壁体的形成包括在栅极堆叠的外表面和侧壁间隔层上形成第一侧壁形成层，将半导体器件暴露于单个晶片反应器中的加热循环，以及形成第二侧壁 在第一侧壁形成层的外表面上形成层。 第二侧壁形成层的形成发生在基本上最小化部分形成的半导体器件的至少一个区域中的掺杂剂损失和失活的环境中。

公开(公告)号：US06737354B2

公开(公告)日：2004-05-18

申请号：US10197989

申请日：2002-07-18

Applicant: Donald S. Miles ,  Douglas T. Grider ,  Chidi P R Chidambaram ,  Amitabh Jain

Inventor： Donald S. Miles ,  Douglas T. Grider ,  Chidi P R Chidambaram ,  Amitabh Jain

IPC: H01L2144

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656

Abstract: An improved source/drain extension process is provided by processing steps (steps A and G) that cover the wafer and dry etching steps (steps D and I) that provide side wall spacers of poly oxide and/or cap oxide from the PMOS gate areas before doing PMOS implanting steps(K and M). The capping of the wafer (step G)with the cap oxide after the NMOS implant also prevents the arsenic from out diffusing from the silicon. Further embodiments include implanting directly on the base.

Abstract translation: 通过覆盖晶片的处理步骤（步骤A和G）和从PMOS栅极区域提供多晶氧化物和/或氧化物半导体的侧壁间隔物的干蚀刻步骤（步骤D和I）提供改进的源极/漏极扩展过程 在进行PMOS植入步骤（K和M）之前。 在NMOS注入之后，具有帽氧化物的晶片（步骤G）的封盖还防止砷从硅扩散出来。 其它实施例包括直接植入基底。

公开(公告)号：US06713360B2

公开(公告)日：2004-03-30

申请号：US10218027

申请日：2002-08-12

Applicant: Amitabh Jain ,  Kaiping Liu ,  Zhiqiang Wu

Inventor： Amitabh Jain ,  Kaiping Liu ,  Zhiqiang Wu

IPC: H01L21331

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/2652 ,  H01L29/1083

Abstract: The present invention provides a method for forming a transistor junction in a semiconductor wafer by implanting a dopant material (116) into the semiconductor wafer, implanting a halo material (110) into the semiconductor wafer (102), selecting a fluorine dose and energy to tailor one or more characteristics of the transistor, implanting fluorine into the semiconductor wafer at the selected dose and energy, activating the dopant material using a thermal process and annealing the semiconductor wafer to remove residual fluorine. The one or more characteristics of the transistor may include halo segregation, halo diffusion, the sharpness of the halo profile, dopant activation, dopant profile sharpness, drive current, bottom wall capacitance or near edge capacitance.

Abstract translation: 本发明提供了一种通过将掺杂剂材料（116）注入到半导体晶片中而在半导体晶片中形成晶体管结的方法，将卤素材料（110）注入到半导体晶片（102）中，选择氟剂量和能量 定制晶体管的一个或多个特性，以选择的剂量和能量将氟注入到半导体晶片中，使用热处理激活掺杂剂材料并退火半导体晶片以除去残留的氟。 晶体管的一个或多个特性可以包括卤素偏析，卤素扩散，晕轮廓的锐度，掺杂剂激活，掺杂剂分布锐度，驱动电流，底壁电容或近边缘电容。

公开(公告)号：US09496359B2

公开(公告)日：2016-11-15

申请号：US13427062

申请日：2012-03-22

Applicant: Brian K. Kirkpatrick ,  Amitabh Jain

Inventor： Brian K. Kirkpatrick ,  Amitabh Jain

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/778

CPC classification number: H01L27/092 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/823864 ,  H01L29/161 ,  H01L29/41775 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/778 ,  H01L29/7833

Abstract: A method of fabricating an integrated circuit includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric. The first dielectric material is etched to form sidewall spacers on sidewalls of the gate stack. A top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material.

Abstract translation: 一种制造集成电路的方法包括：将第一电介质材料沉积在其上具有栅极堆叠的衬底的半导体表面上，其中栅极堆叠包括在栅极电介质上的栅电极。 蚀刻第一电介质材料以在栅叠层的侧壁上形成侧壁间隔物。 通过添加至少一个元件以提供表面转换的侧壁间隔物，将第一介电材料的顶表面化学转化为第二介电材料。 第二电介质材料通过过渡区化学键合到第一介电材料。