公开(公告)号：US20160202723A1

公开(公告)日：2016-07-14

申请号：US14592146

申请日：2015-01-08

Applicant: Apple Inc.

Inventor： Gilbert H. Herbeck ,  Gregoire J. Le Grand de Mercey

IPC: G06F1/12

CPC classification number: G06F1/12

Abstract: Various embodiments of a clock generator are disclosed. An example system may include a functional unit, and a clock generation unit configured to adjust a frequency of an output clock signal responsive to an assertion of an enable signal from the functional unit. The clock generation unit may also be configured to halt the output clock signal responsive to a de-assertion of the enable signal by the functional unit and to restart the output clock signal responsive to a determination that a first predetermined amount of time has elapsed since the output clock signal was halted. The clock generation unit may be further configured to adjust the frequency of the output clock signal responsive to restarting the output clock signal, and to halt the output clock signal responsive to a determination that the frequency of the output clock signal is within a predetermined frequency range that includes the target frequency.

Abstract translation: 公开了时钟发生器的各种实施例。 示例性系统可以包括功能单元，以及时钟生成单元，被配置为响应于来自功能单元的使能信号的断言来调整输出时钟信号的频率。 时钟生成单元还可以被配置为响应于功能单元的使能信号的断言而停止输出时钟信号，并且响应于从第一预定时间量过去的确定重新启动输出时钟信号 输出时钟信号停止。 时钟生成单元还可以被配置为响应于重新启动输出时钟信号而调整输出时钟信号的频率，并响应于输出时钟信号的频率在预定频率范围内的确定而停止输出时钟信号 包括目标频率。

公开(公告)号：US20160094230A1

公开(公告)日：2016-03-31

申请号：US14497376

申请日：2014-09-26

Applicant: Apple Inc.

Inventor： Gilbert H. Herbeck ,  Gregoire J. Le Grand de Mercey ,  Yair R. Koren ,  Jung Wan Kim

IPC: H03L7/081 ,  H03K5/01

CPC classification number: H03L7/0818 ,  H03K5/01 ,  H03L7/0814

Abstract: An apparatus is disclosed in which a clock signal may propagate through a delay circuit. The delay circuit may include a first and a second delay stage, in which each delay stage may be programmable for one of two delay times, depending on a value of a respective control signal to each delay stage. The delay circuit may also include circuitry which may change the value of the respective control signal from a first value to a second value. The circuitry may change the value of the respective control signal responsive to a determination that an output of the first stage and an output of the second stage are equal.

Abstract translation: 公开了一种装置，其中时钟信号可以通过延迟电路传播。 延迟电路可以包括第一和第二延迟级，其中根据对每个延迟级的相应控制信号的值，每个延迟级可以被编程为两个延迟时间中的一个。 延迟电路还可以包括可以将相应控制信号的值从第一值改变到第二值的电路。 响应于第一级的输出和第二级的输出相等的确定，电路可以改变相应控制信号的值。

公开(公告)号：US20160048191A1

公开(公告)日：2016-02-18

申请号：US14459482

申请日：2014-08-14

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Gilbert H. Herbeck ,  Shu-Yi Yu ,  Sebastian Skalberg

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

Abstract: A system and method for managing idleness of functional units in an IC is disclosed. An IC includes a subsystem having a number of functional units and an idle aggregation unit. When a particular functional unit determines that it is idle, it may assert an idle indication to the idle aggregation unit. When the respective idle indications are concurrently asserted for all of the functional units, the idle aggregation unit may assert and provide respective idle request signals to each of the functional units. Responsive to receiving an idle request unit, a given functional unit may provide an acknowledgement signal to the idle aggregation unit if no transactions are incoming. If all functional units have concurrently asserted their respective acknowledgement signals, the idle aggregation unit may provide an indication of the same to a clock gating unit, which may then gate the clock signal(s) received by the functional units.

Abstract translation: 公开了一种用于管理IC中的功能单元的空闲的系统和方法。 IC包括具有多个功能单元和空闲聚合单元的子系统。 当特定功能单元确定它是空闲时，它可以向空闲聚合单元断言空闲指示。 当对于所有功能单元同时断言相应的空闲指示时，空闲汇聚单元可以向每个功能单元断言并提供相应的空闲请求信号。 响应于接收空闲请求单元，如果没有事务进入，则给定功能单元可以向空闲聚合单元提供确认信号。 如果所有功能单元已经同时确定其各自的确认信号，则空闲聚合单元可以向时钟选通单元提供相同的指示，时钟门控单元然后可以对由功能单元接收的时钟信号进行门控。

公开(公告)号：US20160029318A1

公开(公告)日：2016-01-28

申请号：US14444198

申请日：2014-07-28

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Gilbert H. Herbeck

IPC: H04W52/02

CPC classification number: H04W52/0235 ,  H04W52/0212 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/26

Abstract: A method for managing power in a system, in which the system may include a first device configured to transmit serial data and a second device, coupled to the first device. The second device may include a transceiver and interrupt logic, and may be configured to activate the interrupt logic and enable a reduced power mode for the transceiver. Power consumption of the transceiver operating in the reduced power mode may be less than power consumption of the transceiver in an operating mode. The second device may also be configured to assert an interrupt signal responsive to a change in a voltage level of an input of the second device and then de-activate the reduced power mode for the transceiver responsive to the assertion of the interrupt signal.

Abstract translation: 一种用于管理系统中的电力的方法，其中所述系统可以包括被配置为传送串行数据的第一设备和耦合到所述第一设备的第二设备。 第二设备可以包括收发器和中断逻辑，并且可以被配置为激活中断逻辑并使能收发器的降低的功率模式。 以降低功率模式工作的收发器的功耗可能小于工作模式下收发器的功耗。 第二设备还可以被配置为响应于第二设备的输入的电压电平的变化来断言中断信号，然后响应于断言中断信号的断言而使得收发器的功率降低模式失效。

公开(公告)号：US20150347287A1

公开(公告)日：2015-12-03

申请号：US14458949

申请日：2014-08-13

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. De Cesare ,  Anand Dalal

IPC: G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0223 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0673 ,  G06F9/4406 ,  G06F12/0646 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/1032 ,  G11C11/40615 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以对所捕获的传感器数据进行过滤。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。

公开(公告)号：US20140310549A1

公开(公告)日：2014-10-16

申请号：US13861071

申请日：2013-04-11

Applicant: APPLE INC.

Inventor： Gilbert H. Herbeck

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3225 ,  G06F1/3243 ,  G06F5/12 ,  G06F2205/061 ,  G06F2205/126 ,  Y02D10/126 ,  Y02D10/152

Abstract: An apparatus and method for saving power when transmitting data across a clock boundary is disclosed. In one embodiment, an apparatus includes a FIFO coupled to receive data from circuitry in a first clock domain and output data to circuitry in a second clock domain. A first control circuit is responsible for writing data into the FIFO. A second control circuit is responsible for reading data from the FIFO. If the amount of data in the FIFO exceeds a first threshold, a power management circuit may place the first control circuit in a low power state. The second control circuit may monitor the amount of data in the FIFO. If the amount of data in the FIFO falls below a second threshold, it may assert an indication to the power management circuit. Thereafter, the power management circuit may cause the first control circuit to exit the low power state.

Abstract translation: 公开了一种在时钟边界上传输数据时节省电力的装置和方法。 在一个实施例中，一种装置包括FIFO，其耦合以从第一时钟域中的电路接收数据，并将数据输出到第二时钟域中的电路。 第一个控制电路负责将数据写入FIFO。 第二个控制电路负责从FIFO中读取数据。 如果FIFO中的数据量超过第一阈值，则电源管理电路可以将第一控制电路置于低功率状态。 第二控制电路可以监视FIFO中的数据量。 如果FIFO中的数据量低于第二阈值，则它可以向电源管理电路断言一个指示。 此后，电源管理电路可以使第一控制电路退出低功率状态。

公开(公告)号：US11374967B2

公开(公告)日：2022-06-28

申请号：US16276504

申请日：2019-02-14

Applicant: Apple Inc.

Inventor： Zhimin Chen ,  Timothy R. Paaske ,  Gilbert H. Herbeck

IPC: G06F21/64 ,  H04L9/40 ,  G06F21/57 ,  G06F21/71 ,  G06F21/74 ,  G06F12/14

Abstract: A system and method for detecting replay attacks on secure data are disclosed. A system on a chip (SOC) includes a security processor. Blocks of data corresponding to sensitive information are stored in off-chip memory. The security processor uses an integrity data structure, such as an integrity tree, for the blocks. The intermediate nodes of the integrity tree use nonces which have been generated independent of any value within a corresponding block. By using only the nonces to generate tags in the root at the top layer stored in on-chip memory and the nodes of the intermediate layers stored in off-chip memory, an amount of storage used is reduced for supporting the integrity tree. When the security processor detects events which create access requests for one or more blocks, the security processor uses the integrity tree to verify a replay attack has not occurred and corrupted data.

公开(公告)号：US20210333132A1

公开(公告)日：2021-10-28

申请号：US17366459

申请日：2021-07-02

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal ,  Michael F. Culbert

IPC: G01D9/00 ,  G06F13/16 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US11079261B2

公开(公告)日：2021-08-03

申请号：US16689555

申请日：2019-11-20

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G01D9/00 ,  G06F13/16 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US20200149932A1

公开(公告)日：2020-05-14

申请号：US16689555

申请日：2019-11-20

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G01D9/00 ,  G06F1/3293 ,  G06F1/3287 ,  G06F1/3206 ,  G06F13/16

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.