公开(公告)号：US20170372960A1

公开(公告)日：2017-12-28

申请号：US15700631

申请日：2017-09-11

申请人： Applied Materials, Inc.

发明人： Bencherki Mebarki ,  Huixiong Dai ,  Yongmei Chen ,  He Ren ,  Mehul Naik

IPC分类号： H01L21/768 ,  H01L21/3213 ,  H01L23/532

摘要： A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.

公开(公告)号：US11289342B2

公开(公告)日：2022-03-29

申请号：US16901210

申请日：2020-06-15

申请人： Applied Materials, Inc.

发明人： He Ren ,  Jong Mun Kim ,  Maximillian Clemons ,  Minrui Yu ,  Mehul Naik ,  Chentsau Ying

IPC分类号： H01L21/321 ,  H01L21/3213

摘要： Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

公开(公告)号：US11205589B2

公开(公告)日：2021-12-21

申请号：US16594057

申请日：2019-10-06

申请人： APPLIED MATERIALS, INC.

发明人： He Ren ,  Hao Jiang ,  Mehul Naik ,  Srinivas D Nemani ,  Ellie Yieh

IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/768 ,  H01L21/285 ,  H01L21/67 ,  C23C14/58 ,  H01L21/3213 ,  C23C14/16

摘要： Methods and apparatus for lowering resistivity of a metal line, including: depositing a first metal layer atop a second metal layer to under conditions sufficient to increase a grain size of a metal of the first metal layer; etching the first metal layer to form a metal line with a first line edge roughness and to expose a portion of the second metal layer; removing impurities from the metal line by a hydrogen treatment process; and annealing the metal line at a pressure between 760 Torr and 76,000 Torr to reduce the first line edge roughness.

公开(公告)号：US10062607B2

公开(公告)日：2018-08-28

申请号：US15243600

申请日：2016-08-22

申请人： APPLIED Materials, Inc.

发明人： Ismail T. Emesh ,  Roey Shaviv ,  Mehul Naik

IPC分类号： H01L21/76 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76879 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53209 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming metallization in a workpiece includes electrochemically depositing a second metallization layer on the workpiece comprising a nonmetallic substrate having a dielectric layer disposed over a substrate and a continuous first metallization layer disposed on the dielectric layer and having at least one microfeature comprising a recessed structure, wherein the first metallization layer at least partially fills a feature on the workpiece, where the first metallization layer is a cobalt or nickel metal layer, and wherein the second metallization layer is a cobalt or nickel metal layer that is different from the metal of the first metallization layer, electrochemically depositing a copper cap layer after filling the feature, and annealing the workpiece to diffuse the metal of the second metallization layer into the metal of the first metallization layer.

公开(公告)号：US20170309515A1

公开(公告)日：2017-10-26

申请号：US15137245

申请日：2016-04-25

申请人： APPLIED MATERIALS, INC.

发明人： He Ren ,  Jie Zhou ,  Guannan Chen ,  Michael W. Stowell ,  Bencherki Mebarki ,  Mehul Naik ,  Srinivas D. Nemani ,  Nikolaos Bekiaris ,  Zhiyuan Wu

IPC分类号： H01L21/768

CPC分类号： H01L21/76883 ,  H01L21/28556 ,  H01L21/76877 ,  H01L23/53209

摘要： An integrated circuit is fabricated by chemical vapor deposition or atomic layer deposition of a metal film to metal film.

公开(公告)号：US20170047249A1

公开(公告)日：2017-02-16

申请号：US15243600

申请日：2016-08-22

申请人： APPLIED Materials, Inc.

发明人： Ismail T. Emesh ,  Roey Shaviv ,  Mehul Naik

IPC分类号： H01L21/768

CPC分类号： H01L21/76879 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming metallization in a workpiece includes electrochemically depositing a second metallization layer on the workpiece comprising a nonmetallic substrate having a dielectric layer disposed over a substrate and a continuous first metallization layer disposed on the dielectric layer and having at least one microfeature comprising a recessed structure, wherein the first metallization layer at least partially fills a feature on the workpiece, where the first metallization layer is a cobalt or nickel metal layer, and wherein the second metallization layer is a cobalt or nickel metal layer that is different from the metal of the first metallization layer, electrochemically depositing a copper cap layer after filling the feature, and annealing the workpiece to diffuse the metal of the second metallization layer into the metal of the first metallization layer.

摘要翻译： 用于在工件中形成金属化的方法包括在工件上电化学沉积第二金属化层，该第二金属化层包括非金属基底，该非金属基底具有设置在基底上的电介质层和设置在电介质层上的连续的第一金属化层，并且具有至少一个微特征， 其中所述第一金属化层至少部分地填充所述工件上的特征，其中所述第一金属化层是钴或镍金属层，并且其中所述第二金属化层是钴或镍金属层，其不同于 所述第一金属化层在填充所述特征之后电化学沉积铜覆盖层，并且退火所述工件以将所述第二金属化层的金属扩散到所述第一金属化层的金属中。

公开(公告)号：US09570345B1

公开(公告)日：2017-02-14

申请号：US15075039

申请日：2016-03-18

申请人： APPLIED MATERIALS, INC.

发明人： Nikolaos Bekiaris ,  Mehul Naik ,  Zhiyuan Wu

IPC分类号： H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/02074 ,  H01L21/76814 ,  H01L21/76832 ,  H01L21/76883 ,  H01L23/53209

摘要： Resistance increase in Cobalt interconnects due to nitridation occurring during removal of surface oxide from Cobalt interconnects and deposition of Nitrogen-containing film on Cobalt interconnects is solved by a Hydrogen thermal anneal or plasma treatment. Removal of the Nitrogen is through a thin overlying layer which may be a dielectric barrier layer or an etch stop layer.

摘要翻译： 通过氢热退火或等离子体处理，可以解决由于从Cobalt互连中去除表面氧化物时发生的氮化而导致的钴互连的电阻增加和含钴膜在钴互连上的沉积。 通过可以是介电阻挡层或蚀刻停止层的薄的上覆层去除氮。

公开(公告)号：US09514953B2

公开(公告)日：2016-12-06

申请号：US14541978

申请日：2014-11-14

申请人： Applied Materials, Inc.

发明人： Chia-Ling Kao ,  Sean Kang ,  Jeremiah T. Pender ,  Srinivas D. Nemani ,  He Ren ,  Mehul Naik

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  H01L21/02 ,  H01J37/32 ,  H01L21/768

CPC分类号： H01L21/31116 ,  H01J37/32449 ,  H01J37/32477 ,  H01J37/32834 ,  H01J37/32871 ,  H01L21/02063 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829

摘要： Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.

摘要翻译： 本文描述的实施方式通常涉及半导体制造，更具体地涉及使用非碳基方法蚀刻设置在基板上的低k电介质阻挡层的方法。 在一个实施方案中，提供了用于蚀刻阻挡层低k层的方法。 该方法包括（a）将低k阻挡层的表面暴露于处理气体混合物以修饰低k阻挡层的至少一部分，和（b）化学蚀刻低k阻挡层的修饰部分 通过将改性部分暴露于化学蚀刻气体混合物，其中化学蚀刻气体混合物至少包含铵气体和三氟化氮气体，或至少包含氢气和三氟化氮气体。

公开(公告)号：US20150147879A1

公开(公告)日：2015-05-28

申请号：US14483578

申请日：2014-09-11

申请人： Applied Materials, Inc.

发明人： Amit Chatterjee ,  Geetika Bajaj ,  Pramit Manna ,  He Ren ,  Tapash Chakraborty ,  Srinivas D. Nemani ,  Mehul Naik ,  Robert Jan visser ,  Abhijit Basu Mallick

IPC分类号： H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76838 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of depositing thin, low dielectric constant layers that are effective diffusion barriers on metal interconnects of semiconductor circuits are described. A self-assembled monolayer (SAM) of molecules each having a head moiety and a tail moiety are deposited on the metal. The SAM molecules self-align, wherein the head moiety is formulated to selectively bond to the metal layer leaving the tail moiety disposed at a distal end of the molecule. A dielectric layer is subsequently deposited on the SAM, chemically bonding to the tail moiety of the SAM molecules.

摘要翻译： 描述了在半导体电路的金属互连上沉积有效扩散阻挡层的薄的低介电常数层的方法。 每个具有头部和尾部的分子的自组装单层（SAM）沉积在金属上。 SAM分子自对准，其中头部部分被配制成选择性地键合到金属层，离开设置在分子远端的尾部。 随后在SAM上沉积介电层，化学键合到SAM分子的尾部。

公开(公告)号：US20230045689A1

公开(公告)日：2023-02-09

申请号：US17968201

申请日：2022-10-18

申请人： Applied Materials, Inc.

发明人： Hao Jiang ,  Chi Lu ,  He Ren ,  Chi-I Lang ,  Ho-yung David Hwang ,  Mehul Naik

IPC分类号： H01L21/768 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/027

摘要： A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.