公开(公告)号：US07477073B1

公开(公告)日：2009-01-13

申请号：US11454316

申请日：2006-06-16

申请人： Tim Tuan ,  Arifur Rahman ,  Satyaki Das ,  Sean W. Kao

发明人： Tim Tuan ,  Arifur Rahman ,  Satyaki Das ,  Sean W. Kao

IPC分类号： H03K19/177 ,  H03K19/0175

CPC分类号： H03K19/17736 ,  H03K19/17784

摘要： A PLD utilizes a heterogeneous architecture to reduce power consumption of its active resources. The PLD's programmable resources are divided into a first partition and a second partition, where the resources of the first partition are optimized for low power consumption and the resources of the second partition are optimized for high performance. Portions of a user design containing non-critical timing paths are mapped to and implemented by the resources of the power-optimized first partition, and portions of the user design containing critical timing paths are mapped to and implemented by the resources of the performance-optimized second partition.

摘要翻译： PLD利用异构架构来降低其活动资源的功耗。 PLD的可编程资源分为第一分区和第二分区，其中第一分区的资源被优化用于低功耗，并且第二分区的资源被优化用于高性能。 包含非关键定时路径的用户设计的部分被映射到由功率优化的第一分区的资源并由其实现，并且包含关键定时路径的用户设计的部分被映射到由性能优化的资源实现 第二分区。

公开(公告)号：US20070287224A1

公开(公告)日：2007-12-13

申请号：US11737598

申请日：2007-04-19

申请人： Syed Alam ,  Ibrahim Elfadel ,  Kathryn Guarini ,  Meikei Ieong ,  Prabhakar Kudva ,  David Kung ,  Mark Lavin ,  Arifur Rahman

发明人： Syed Alam ,  Ibrahim Elfadel ,  Kathryn Guarini ,  Meikei Ieong ,  Prabhakar Kudva ,  David Kung ,  Mark Lavin ,  Arifur Rahman

IPC分类号： H01L21/02

CPC分类号： H01L27/0688 ,  H01L21/2007 ,  H01L21/84 ,  H01L27/1203

摘要： A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

摘要翻译： 三维（3D）集成电路（IC），3D IC芯片和制造3D IC芯片的方法。 该芯片包括多层电路，例如硅绝缘体（SOI）CMOS IC层，每层包括电路元件。 这些层可以平行地形成，并且一层附着到另一层以形成层叠的3D芯片。

公开(公告)号：US20060033110A1

公开(公告)日：2006-02-16

申请号：US10919121

申请日：2004-08-16

申请人： Syed Alam ,  Ibrahim Elfadel ,  Kathryn Guarini ,  Meikei Ieong ,  Prabhakar Kudva ,  David Kung ,  Mark Lavin ,  Arifur Rahman

发明人： Syed Alam ,  Ibrahim Elfadel ,  Kathryn Guarini ,  Meikei Ieong ,  Prabhakar Kudva ,  David Kung ,  Mark Lavin ,  Arifur Rahman

IPC分类号： H01L29/04

CPC分类号： H01L27/0688 ,  H01L21/2007 ,  H01L21/84 ,  H01L27/1203

摘要： A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

摘要翻译： 三维（3D）集成电路（IC），3D IC芯片和3D IC芯片的制造方法。 该芯片包括多层电路，例如硅绝缘体（SOI）CMOS IC层，每层包括电路元件。 这些层可以平行地形成，并且一层附着到另一层以形成层叠的3D芯片。

公开(公告)号：US20050230271A1

公开(公告)日：2005-10-20

申请号：US11033046

申请日：2005-01-11

申请人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

发明人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

IPC分类号： G01N27/26 ,  G01N27/414

CPC分类号： G01N27/4145 ,  G01N27/4148

摘要： Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, VT.

摘要翻译： 可以使用与浮置栅极离子敏感场效应晶体管（FGISFET）的浮动栅极电耦合的感测材料的特定离子相互作用来感测目标材料。 例如，FGISFET可以使用浮动栅极场效应晶体管的浮动栅极（例如，先前证明的）基于离子相互作用的感测技术。 浮动栅极可以用作探针和将化学和/或生物信号转换成电信号的接口，这可以通过监测器件的阈值电压V T T的变化来测量。

公开(公告)号：US06859066B1

公开(公告)日：2005-02-22

申请号：US10377320

申请日：2003-02-28

申请人： Arifur Rahman ,  William Andrews ,  Mou C. Lin

发明人： Arifur Rahman ,  William Andrews ,  Mou C. Lin

IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/017581 ,  H03K19/1778 ,  H03K19/17788

摘要： A bank of input/output buffers are configured such that each input buffer in the bank may select from a plurality of voltage references during single-ended operation. Similarly, the pad associated with each input buffer may serve to supply one of the voltage references for other input buffers within the bank.

摘要翻译： 一组输入/输出缓冲器被配置为使得单行中的每个输入缓冲器可以在单端操作期间从多个电压基准中选择。 类似地，与每个输入缓冲器相关联的焊盘可以用于为bank内的其它输入缓冲器提供一个电压基准。

公开(公告)号：US09129935B1

公开(公告)日：2015-09-08

申请号：US13646477

申请日：2012-10-05

申请人： Karthik Chandrasekar ,  Arifur Rahman ,  Jeffrey Tyhach

发明人： Karthik Chandrasekar ,  Arifur Rahman ,  Jeffrey Tyhach

IPC分类号： H01L23/48 ,  H01L49/02 ,  H01L21/50 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L28/40 ,  H01L21/486 ,  H01L21/50 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/642 ,  H01L24/05 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/1411 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157

摘要： A multi-chip package that includes multiple integrated circuits is provided. An integrated circuit in the multi-chip package may be mounted on an interposer. The interposer may be mounted on a package substrate. The integrated circuit may have internal power supply terminals coupled to on-package decoupling (OPD) capacitor circuitry that are formed as part of the package substrate. The power supply terminals on the integrated circuit may be coupled to conductive routing paths and through-silicon vias (TSVs) in the interposer via microbumps. The through-silicon vias in the interposer may be coupled to the OPD capacitor circuitry via flip-chip bumps. The conductive routing paths and the TSVs in the interposer may be coupled to the internal integrated circuit power supply terminals in a way that minimizes power supply resonance noise.

摘要翻译： 提供了包括多个集成电路的多芯片封装。 多芯片封装中的集成电路可以安装在插入器上。 插入器可以安装在封装衬底上。 集成电路可以具有耦合到作为封装衬底的一部分形成的封装间去耦（OPD）电容器电路的内部电源端子。 集成电路上的电源端子可以经由微注入件与中介层中的导电布线路径和穿硅通孔（TSV）耦合。 插入器中的穿硅通孔可以通过倒装芯片凸块耦合到OPD电容器电路。 插入器中的导电布线路径和TSV可以以最小化电源谐振噪声的方式耦合到内部集成电路电源端子。

公开(公告)号：US08987868B1

公开(公告)日：2015-03-24

申请号：US12392065

申请日：2009-02-24

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H01L29/40

CPC分类号： H01L23/525 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5286 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/014

摘要： Method and apparatus for programmable heterogeneous integration of stacked semiconductor die are described. In some examples, a semiconductor device includes a first integrated circuit (IC) die including through-die vias (TDVs); a second IC die vertically stacked with the first IC die, the second IC die including inter-die contacts electrically coupled to the TDVs; the first IC die including heterogeneous power supplies and a mask-programmable interconnect, the mask-programmable interconnect mask-programmed to electrically couple a plurality of the heterogeneous power supplies to the TDVs; and the second IC die including active circuitry, coupled to the inter-die contacts, configured to operate using the plurality of heterogeneous power supplies provided by the TDVs.

摘要翻译： 描述了用于层叠半导体管芯的可编程异构集成的方法和装置。 在一些示例中，半导体器件包括包括通孔（TDV）的第一集成电路（IC）裸片; 与所述第一IC管芯垂直堆叠的第二IC管芯，所述第二IC管芯包括电连接到所述TDV的管芯间接触; 所述第一IC芯片包括异质电源和掩模可编程互连，所述掩模可编程互连掩模编程以将多个所述异质电源电耦合到所述TDV; 并且所述第二IC裸片包括耦合到所述管芯间触点的有源电路，其被配置为使用由所述TDV提供的所述多个异质电源进行操作。

公开(公告)号：US08933447B1

公开(公告)日：2015-01-13

申请号：US12778962

申请日：2010-05-12

申请人： Arifur Rahman ,  Ramakrishna K. Tanikella ,  Trevor J. Bauer ,  Brian C. Gaide ,  Steven P. Young

发明人： Arifur Rahman ,  Ramakrishna K. Tanikella ,  Trevor J. Bauer ,  Brian C. Gaide ,  Steven P. Young

IPC分类号： H01L23/02 ,  H01L23/34

CPC分类号： G01R31/318513 ,  G01R31/318516 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A method and apparatus to test the inter-die interface between two or more semiconductor die in die stacking applications, where a mismatch exists between the number of input and output pads on a base die and the number of input and output pads on a stacked die. In a first embodiment, a number of through-die vias (TDVs) may be used to implement inter-die signal paths using standard or flexible design rules to maintain statistical TDV yield despite the lack of continuity verification of the inter-die signals paths. In alternate embodiments, programmable multiplexers may be utilized to share one or more inter-die connections between the base die and the one or more stacked die so as to facilitate testing and normal operation of each inter-die connection. In other embodiments, spare TDVs are utilized only during test operations, so as to accommodate the mismatch. In yet other embodiments, built-in-test (BIT) circuits are configured to perform logic operations using a plurality of inter-die input/output (I/O) signals to eliminate the need to implement an identical number of input and output ports between the base die and the one or more stacked die to facilitate inter-die testing.

摘要翻译： 一种用于在芯片堆叠应用中测试两个或更多个半导体管芯之间的管芯间界面的方法和装置，其中基底管芯上的输入和输出焊盘的数量与堆叠管芯上的输入和输出焊盘的数量之间存在不匹配 。 在第一实施例中，尽管缺少芯片间信号路径的连续性验证，但是使用标准或灵活的设计规则可以使用多个贯通管芯通孔（TDV）来实现管芯间信号路径，以维持统计TDV产量。 在替代实施例中，可以使用可编程多路复用器来共享基模和一个或多个堆叠管芯之间的一个或多个管芯间连接，以便于每个管芯间连接的测试和正常工作。 在其他实施例中，仅在测试操作期间使用备用TDV，以便适应不匹配。 在其他实施例中，内置测试（BIT）电路被配置为使用多个管芯间输入/输出（I / O）信号来执行逻辑操作，以消除实现相同数量的输入和输出端口的需要 在基模和一个或多个堆叠的模具之间，以促进模间测试。

公开(公告)号：US08415783B1

公开(公告)日：2013-04-09

申请号：US11973245

申请日：2007-10-04

申请人： Arifur Rahman ,  Raghunandan Chaware

发明人： Arifur Rahman ,  Raghunandan Chaware

IPC分类号： H01L23/02 ,  H01L23/34

CPC分类号： H01L23/3107 ,  G01R31/2884 ,  H01L21/561 ,  H01L22/32 ,  H01L23/3135 ,  H01L23/36 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/00

摘要： A packaged integrated circuit (“IC”) has a daughter IC die stacked on a backside of a parent IC die. Backside fill material is applied to the backside of the parent IC die to provide a planarized surface.

摘要翻译： 封装集成电路（IC）具有堆叠在母IC芯片的背面的子IC芯片。 将背面填充材料施加到母IC芯片的背面以提供平坦化表面。

公开(公告)号：US08082537B1

公开(公告)日：2011-12-20

申请号：US12361115

申请日：2009-01-28

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： G06F17/50 ,  H01L29/06 ,  H01L29/40

CPC分类号： G06F17/5054 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13027 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： Examples of the invention relate to a method, apparatus, and computer readable medium for designing a mother integrated circuit (IC) configured for stacking with at least one daughter IC. A layout of the mother IC includes at least one interface tile having an electrical configuration for communicating with interface logic of the daughter IC. The method includes: obtaining design rules for through die vias (TDVs) to be formed in the mother IC for implementing connections between the at least one interface tile and a physical interface of the daughter IC; defining a layout of the TDVs in the mother IC according to the design rules; and defining at least one mask for programming interconnect on the mother IC to physically connect the TDVs between the at least one interface tile and the physical interface of the daughter IC without changing the electrical configuration of the at least one interface tile.

摘要翻译： 本发明的实例涉及用于设计配置为与至少一个子IC堆叠的母集成电路（IC）的方法，装置和计算机可读介质。 母IC的布局包括至少一个接口瓦片，其具有用于与子IC的接口逻辑通信的电气配置。 该方法包括：获得要在母IC中形成的通孔（TDV）的设计规则，用于实现至少一个接口片和子IC的物理接口之间的连接; 根据设计规则定义母IC中的TDV布局; 以及定义用于在所述母IC上编程互连的至少一个掩模，以物理地连接所述至少一个接口瓦片和所述子IC的物理接口之间的TDV，而不改变所述至少一个接口瓦片的电气配置。