公开(公告)号：US07098507B2

公开(公告)日：2006-08-29

申请号：US10879480

申请日：2004-06-30

申请人： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Brian Doyle ,  Suman Datta ,  Vivek K. De

发明人： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Brian Doyle ,  Suman Datta ,  Vivek K. De

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/39

CPC分类号： H01L29/785 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7841

摘要： A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

公开(公告)号：US20060128131A1

公开(公告)日：2006-06-15

申请号：US11335103

申请日：2006-01-18

申请人： Peter Chang ,  Brian Doyle

发明人： Peter Chang ,  Brian Doyle

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66795

摘要： A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device.

公开(公告)号：US07042009B2

公开(公告)日：2006-05-09

申请号：US10883183

申请日：2004-06-30

申请人： Mohamad A. Shaheen ,  Brian Doyle ,  Suman Dutta ,  Robert S. Chau ,  Peter Tolchinsky

发明人： Mohamad A. Shaheen ,  Brian Doyle ,  Suman Dutta ,  Robert S. Chau ,  Peter Tolchinsky

IPC分类号： H01L27/01 ,  H01L29/04

CPC分类号： H01L29/785 ,  H01L21/76243 ,  H01L21/76254 ,  H01L21/76256 ,  H01L29/045 ,  H01L29/66772

摘要： A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.

摘要翻译： 高迁移率半导体组件。 在一个示例性方面，高迁移率半导体组件包括具有位于第一衬底上的<110>晶面位置处的第一参考取向的第一衬底和形成在第一衬底顶部上的第二衬底。 第二衬底具有位于第二衬底上的<100>晶面位置处的第二参考取向，其中第一参考取向与第二参考取向对准。 在另一示例性方面，第二衬底具有位于第二衬底上的<110>晶面位置处的第二参考取向，其中第二衬底形成在第一衬底上，第二参考取向通过 约45度。

公开(公告)号：US20060071275A1

公开(公告)日：2006-04-06

申请号：US10956279

申请日：2004-09-30

申请人： Justin Brask ,  Brian Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

发明人： Justin Brask ,  Brian Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US20060051957A1

公开(公告)日：2006-03-09

申请号：US10936114

申请日：2004-09-07

申请人： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Brian Doyle ,  Robert Chau

发明人： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Brian Doyle ,  Robert Chau

IPC分类号： H01L21/4763

CPC分类号： H01L21/82385 ,  H01L21/28114 ,  H01L21/30608 ,  H01L21/823828 ,  H01L29/42376 ,  H01L29/66545 ,  Y10S438/926

摘要： A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider than the first layer. After the sacrificial structure is removed to generate a trench, a metal gate electrode is formed within the trench.

摘要翻译： 描述制造半导体器件的方法。 该方法包括在衬底上形成介电层和包括第一层和第二层的牺牲结构，使得第二层形成在第一层上并且比第一层更宽。 在除去牺牲结构以产生沟槽之后，在沟槽内形成金属栅电极。

公开(公告)号：US06998686B2

公开(公告)日：2006-02-14

申请号：US10230944

申请日：2002-08-28

申请人： Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

发明人： Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

IPC分类号： H01L29/78

CPC分类号： H01L29/665 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

摘要： Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer.The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers. During implant and anneal processes, the polysilicon layer acts as a protective mask over the metallic layers to protect an underlying silicon substrate from interacting with dopants used during the implant process.

摘要翻译： 描述了具有多层栅电极结构的CMOS晶体管结构和制造方法。 栅电极结构具有三层金属栅电极和多晶硅层。 第一金属层用作阻挡层以防止第二金属层与下面的电介质反应。 第二金属层用于设定栅电极结构的功函数。 第三金属层用作阻挡第二金属层与多晶硅层反应的屏障。

公开(公告)号：US20060014331A1

公开(公告)日：2006-01-19

申请号：US10879480

申请日：2004-06-30

申请人： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Brian Doyle ,  Suman Datta ,  Vivek De

发明人： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Brian Doyle ,  Suman Datta ,  Vivek De

IPC分类号： H01L21/84

CPC分类号： H01L29/785 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7841

摘要： A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

摘要翻译： 浮体动态随机存取存储器件可以包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁。 可以在半导体主体的顶表面和半导体本体的横向相对的侧壁上形成栅介质层。 栅极电极可以形成在半导体本体的顶表面上的栅极电介质上并与半导体本体的横向相对的侧壁上的栅电介质相邻。 栅电极可能仅部分地耗尽半导体本体的区域，并且部分耗尽的区域可以用作逻辑状态的存储节点。

公开(公告)号：US06974733B2

公开(公告)日：2005-12-13

申请号：US10463080

申请日：2003-06-16

申请人： Boyan Boyanov ,  Brian Doyle ,  Jack Kavalieros ,  Anand Murthy ,  Robert Chau

发明人： Boyan Boyanov ,  Brian Doyle ,  Jack Kavalieros ,  Anand Murthy ,  Robert Chau

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/338

CPC分类号： H01L29/7842 ,  H01L29/1054 ,  H01L29/66666 ,  H01L29/7827

摘要： There is disclosed an apparatus including a straining substrate, a device over the substrate including a channel, wherein the straining substrate strains the device in a direction substantially perpendicular to a direction of current flow in the channel.

摘要翻译： 公开了一种装置，包括应变基片，包括通道的衬底上的器件，其中应变衬底沿着基本上垂直于沟道中的电流方向的方向施加器件。

公开(公告)号：US20050156171A1

公开(公告)日：2005-07-21

申请号：US11023881

申请日：2004-12-27

申请人： Justin Brask ,  Brian Doyle ,  Mark Doczy ,  Robert Chau

发明人： Justin Brask ,  Brian Doyle ,  Mark Doczy ,  Robert Chau

IPC分类号： H01L21/336 ,  H01L21/77 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/49 ,  H01L29/786 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66795

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are uniformed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US20050136584A1

公开(公告)日：2005-06-23

申请号：US10747321

申请日：2003-12-23

申请人： Boyan Boyanov ,  Anand Murthy ,  Brian Doyle ,  Robert Chau

发明人： Boyan Boyanov ,  Anand Murthy ,  Brian Doyle ,  Robert Chau

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L31/0328 ,  H01L21/8238

CPC分类号： H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

摘要： Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

摘要翻译： 本发明的各种实施例涉及一种CMOS器件，其具有（1）选择性地沉积在渐变硅锗衬底的第一区域上的硅材料的NMOS沟道，使得选择性沉积的硅材料经历由晶格间隔引起的拉伸应变 硅材料小于第一区域处的渐变硅锗衬底材料的晶格间距，以及（2）选择性地沉积在衬底的第二区域上的硅锗材料的PMOS沟道，使得选择性沉积的硅锗材料经历 由选择性沉积的硅锗材料的晶格间距引起的压缩应变大于第二区域处的分级硅锗衬底材料的晶格间距。