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105 条记录 (耗时 0.034 秒)

    Self-healing chip-to-chip interface
    21.
    发明授权
    Self-healing chip-to-chip interface 失效
    自愈芯片到芯片的接口

    公开(公告)号：US07362697B2

    公开(公告)日：2008-04-22

    申请号：US10339757

    申请日：2003-01-09

    申请人： Wiren Dale Becker ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Anand Haridass ,  Robert James Reese

    发明人： Wiren Dale Becker ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Anand Haridass ,  Robert James Reese

    IPC分类号： G01R31/08

    CPC分类号： H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

    摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。

    Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules
    22.
    发明申请
    Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules 有权
    通过/ BSM模式优化，可以降低单个和多个芯片模块上的直流梯度和引脚电流密度

    公开(公告)号：US20070022398A1

    公开(公告)日：2007-01-25

    申请号：US11184350

    申请日：2005-07-19

    申请人： Anand Haridass ,  Andreas Huber ,  Erich Klink ,  Thomas Strach ,  Jochen Supper

    发明人： Anand Haridass ,  Andreas Huber ,  Erich Klink ,  Thomas Strach ,  Jochen Supper

    IPC分类号： G06F17/50 ,  H01L21/00

    CPC分类号： H01L23/49833 ,  G06F17/5068 ,  H01L23/50 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011

    摘要： A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while providing a common electrical ground for both voltage domains. The integrated circuit chip may be a microprocessor having a nominal operating voltage, and the different voltages of the two voltage domains are both within the tolerance range of the nominal operating voltage but one of the voltage domains is aligned with a high power density area of the microprocessor (e.g., the microprocessor core) and provides a slightly greater voltage. The higher power voltage domain preferably has a ratio of voltage pins to ground pins that is greater than one.

    摘要翻译： 通过将两个不同的电压域分配给载体的接触表面的两个分开的区域，同时为两个电压域提供公共电接地来设计诸如集成电路芯片的电子装置的载体。 集成电路芯片可以是具有额定工作电压的微处理器，并且两个电压域的不同电压都在标称工作电压的公差范围内，但是一个电压域与高功率密度区域 微处理器（例如，微处理器内核）并提供略高的电压。 较高的电源电压域优选地具有大于1的电压引脚与接地引脚的比率。

    Circuit manufacturing and design techniques for reference plane voids with strip segment
    26.
    发明授权
    Circuit manufacturing and design techniques for reference plane voids with strip segment 失效
    具有带段的参考平面空隙的电路制造和设计技术

    公开(公告)号：US08625300B2

    公开(公告)日：2014-01-07

    申请号：US13603761

    申请日：2012-09-05

    申请人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    发明人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    IPC分类号： H05K1/14

    CPC分类号： G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

    摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

    摘要翻译： 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

    Noise Coupling Reduction and Impedance Discontinuity Control in High-Speed Ceramic Modules
    27.
    发明申请
    Noise Coupling Reduction and Impedance Discontinuity Control in High-Speed Ceramic Modules 有权
    高速陶瓷模块的噪声耦合降低和阻抗不连续控制

    公开(公告)号：US20120204141A1

    公开(公告)日：2012-08-09

    申请号：US13449732

    申请日：2012-04-18

    申请人： Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

    发明人： Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5036 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0224 ,  H05K3/4629 ,  H05K2201/09236 ,  H05K2201/09681 ,  H01L2924/00

    摘要： A method reduces coupling noise and controls impedance discontinuity in ceramic packages by: providing at least one reference mesh layer; providing a plurality of signal trace layers, with each signal layer having one or more signal lines and the reference mesh layer being adjacent to one or more of the signal layers; disposing a plurality of vias through the at least one reference mesh layer, with each via providing a voltage (Vdd) power connection or a ground (Gnd) connection; selectively placing via-connected coplanar-type shield (VCS) lines relative to the signal lines, with a first VCS line extended along a first side of a first signal line and a second VCS line extended along a second, opposing side of said first signal line. Each of the VCS lines interconnect with and extend past one or more vias located within a directional path along which the VCS lines extends.

    摘要翻译： 一种方法通过以下方式减少耦合噪声并控制陶瓷封装中的阻抗不连续性：提供至少一个参考网格层; 提供多个信号迹线层，其中每个信号层具有一个或多个信号线，并且所述参考网格层与所述信号层中的一个或多个相邻; 通过所述至少一个参考网格层布置多个通孔，其中每个通孔提供电压（Vdd）电源连接或接地（Gnd）连接; 选择性地将通过连接的共面型屏蔽（VCS）线相对于信号线放置，其中第一VCS线沿着第一信号线的第一侧延伸，并且第二VCS线沿着所述第一信号的第二相对侧延伸 线。 VCS线路中的每一条与位于VCS线延伸的定向路径内的一个或多个通孔相互连接并延伸。

    Reference plane voids with strip segment for improving transmission line integrity over vias
    28.
    发明授权
    Reference plane voids with strip segment for improving transmission line integrity over vias 失效
    具有带段的参考平面空隙，以改善通孔上的传输线完整性

    公开(公告)号：US07821796B2

    公开(公告)日：2010-10-26

    申请号：US12015543

    申请日：2008-01-17

    申请人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    发明人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    IPC分类号： H05K1/11

    CPC分类号： G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

    摘要： Reference plane voids with a strip segment for improving transmission line integrity over vias permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

    摘要翻译： 具有用于改善通孔上的传输线完整性的带段的参考平面空隙允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

    Statistical switched capacitor droop sensor for application in power distribution noise mitigation
    29.
    发明授权
    Statistical switched capacitor droop sensor for application in power distribution noise mitigation 有权
    统计开关电容器下垂传感器，用于配电噪声抑制

    公开(公告)号：US07818599B2

    公开(公告)日：2010-10-19

    申请号：US11869186

    申请日：2007-10-09

    申请人： Anand Haridass ,  Colm B. O'Reilly ,  Roger D. Weekly

    发明人： Anand Haridass ,  Colm B. O'Reilly ,  Roger D. Weekly

    IPC分类号： G06F1/26

    CPC分类号： G06F1/28

    摘要： A circuit and a method for detecting noise events in a system with time variable operating points is provided. A switched capacitor filter comprising a plurality of capacitor units, samples a first voltage to determine an average of a set of voltage measurements, forming an average voltage. A filter control unit controls the plurality of capacitor units in the switched capacitor filter. A comparing unit compares the average voltage to the first voltage to form a comparison. A signaling unit generates a signal to instruct circuits in a processor to initiate actions to keep the first voltage from drooping below a threshold level in response to the comparison.

    摘要翻译： 提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路和方法。 一种开关电容滤波器，包括多个电容器单元，对第一电压进行采样，以确定一组电压测量的平均值，形成平均电压。 滤波器控制单元控制开关电容滤波器中的多个电容器单元。 比较单元将平均电压与第一电压进行比较以形成比较。 信号单元产生信号以指示处理器中的电路响应于比较而发起动作以使第一电压不会下降到低于阈值水平。

    Power grid structure to optimize performance of a multiple core processor
    30.
    发明授权
    Power grid structure to optimize performance of a multiple core processor 失效
    电网结构优化多核处理器的性能

    公开(公告)号：US07667470B2

    公开(公告)日：2010-02-23

    申请号：US12143911

    申请日：2008-06-23

    申请人： Jean Audet ,  Louis B. Capps, Jr. ,  Glenn G. Daves ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

    发明人： Jean Audet ,  Louis B. Capps, Jr. ,  Glenn G. Daves ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

    IPC分类号： G01R31/08 ,  G06F19/00

    CPC分类号： G06F1/3203 ,  G06F1/26 ,  G06F1/3296 ,  H01L23/50 ,  H01L2924/0002 ,  Y02D10/172 ,  H01L2924/00

    摘要： A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.

    摘要翻译： 减少数量的电压调节器模块为封装提供了减少的电源电压数量。 该封装包括用于每个电压调节器模块的电压平面。 管芯上的每个核心或其他部件连接到封装上的开关，并且每个开关电连接到所有电压平面。 晶圆级测试确定优化每个核心或其他组件的性能的电压。 给定这些电压值，工程师可以确定电压调节器模块的电压设置以及要连接到哪些电压调节器模块的哪些核心。 数据库存储电压设置数据，例如每个组件的最佳电压，开关值或每个电压调节器模块的电压设置。 工程线可以永久地设置每个开关以定制每个芯或其他部件的电压供应。