公开(公告)号：US09082746B2

公开(公告)日：2015-07-14

申请号：US13350987

申请日：2012-01-16

申请人： Martin Poelzl

发明人： Martin Poelzl

IPC分类号： H01L29/66 ,  H01L21/311 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L21/033 ,  H01L21/768 ,  H01L29/417

CPC分类号： H01L29/66348 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/76897 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/6634 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A semiconductor body component has a first surface and is comprised of a first semiconductor material extending to the first surface. At least one trench extends from the first surface into the semiconductor body and includes a gate electrode insulated from the semiconductor body and arranged below the first surface. A second insulation layer is formed on the first surface with a recess that overlaps in projection onto the first surface with the conductive region. A mask region is formed in the recess, and the second insulation layer is etched selectively to the mask region and the semiconductor body to expose the semiconductor body at the first surface. A third insulation layer is deposited on the first surface, and the third insulation layer is etched so that a semiconductor mesa of the semiconductor body arranged next to the at least one trench is exposed at the first surface.

摘要翻译： 半导体主体部件具有第一表面，并且包括延伸到第一表面的第一半导体材料。 至少一个沟槽从第一表面延伸到半导体本体中，并且包括与半导体本体绝缘并布置在第一表面下方的栅电极。 第二绝缘层在第一表面上形成有与导电区域在第一表面上的突起重叠的凹部。 在凹部中形成掩模区域，并且第二绝缘层被选择性地蚀刻到掩模区域和半导体本体以在第一表面处露出半导体本体。 在第一表面上沉积第三绝缘层，并且蚀刻第三绝缘层，使得布置在至少一个沟槽旁边的半导体本体的半导体台面在第一表面处露出。

公开(公告)号：US08193559B2

公开(公告)日：2012-06-05

申请号：US13081642

申请日：2011-04-07

申请人： Oliver Haeberlen ,  Walter Rieger ,  Martin Vielemeyer ,  Lutz Goergens ,  Martin Poelzl ,  Milko Paolucci ,  Johannes Schoiswohl ,  Joachim Krumrey ,  Sonja Krumrey, legal representative

发明人： Oliver Haeberlen ,  Walter Rieger ,  Martin Vielemeyer ,  Lutz Goergens ,  Martin Poelzl ,  Milko Paolucci ,  Johannes Schoiswohl ,  Joachim Krumrey

IPC分类号： H01L29/66

CPC分类号： H01L23/495 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L28/40 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0856 ,  H01L29/407 ,  H01L29/41 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7806 ,  H01L29/7809 ,  H01L29/781 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/37099

摘要： One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.

摘要翻译： 一个方面是单片半导体开关和制造方法。 一个实施例提供具有第一n型沟道FET和第二n型沟道FET的半导体管芯。 第一n型沟道FET的源极和第二n型沟道FET的漏极分别电耦合到半导体管芯的第一侧的至少一个接触区域。 第一n型沟道FET的漏极，第一n型沟道FET的栅极，第二n型沟道FET的源极和第二n型沟道FET的栅极电耦合到接触区域 半导体管芯的与第一侧相对的第二侧。 第一n型沟道FET的漏极，第一n型沟道FET的栅极，第二n型沟道FET的源极和第二n型沟道FET的栅极的接触面积 分别电分离。

公开(公告)号：US08097916B2

公开(公告)日：2012-01-17

申请号：US11781582

申请日：2007-07-23

申请人： Martin Poelzl

发明人： Martin Poelzl

IPC分类号： H01L29/66

CPC分类号： H01L29/7811 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66696 ,  H01L29/66734 ,  H01L29/7813

摘要： A method for insulating a semiconducting material in a trench from a substrate, wherein the trench is formed in the substrate and comprising an upper portion and a lower portion, the lower portion being lined with a first insulating layer and filled, at least partially, with a semiconducting material, comprises an isotropic etching of the substrate and the semiconducting material, and forming a second insulating layer in the trench, wherein the second insulating layer covers, at least partially, the substrate and the semiconducting material.

摘要翻译： 一种用于从衬底绝缘的沟槽中的半导体材料的方法，其中所述沟槽形成在所述衬底中并且包括上部和下部，所述下部衬有第一绝缘层，并且至少部分地用 半导体材料包括衬底和半导体材料的各向同性蚀刻，以及在沟槽中形成第二绝缘层，其中第二绝缘层至少部分地覆盖衬底和半导体材料。

公开(公告)号：US20090291543A1

公开(公告)日：2009-11-26

申请号：US12427098

申请日：2009-04-21

申请人： Martin Poelzl

发明人： Martin Poelzl

IPC分类号： H01L21/76

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734

摘要： A method for manufacturing a field plate in a trench of a power transistor in a substrate of a first conductivity type is disclosed. The trench is formed in a first main surface of the substrate.

摘要翻译： 公开了一种在第一导电类型的衬底中的功率晶体管的沟槽中制造场板的方法。 沟槽形成在基板的第一主表面中。

公开(公告)号：US08946767B2

公开(公告)日：2015-02-03

申请号：US13487999

申请日：2012-06-04

申请人： Oliver Haeberlen ,  Walter Rieger ,  Martin Vielemeyer ,  Lutz Goergens ,  Martin Poelzl ,  Milko Paolucci ,  Johannes Schoiswohl ,  Sonja Krumrey

发明人： Oliver Haeberlen ,  Walter Rieger ,  Martin Vielemeyer ,  Lutz Goergens ,  Martin Poelzl ,  Milko Paolucci ,  Johannes Schoiswohl ,  Joachim Krumrey

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8238 ,  H01L49/02 ,  H01L23/492 ,  H01L23/00 ,  H01L23/495 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/41 ,  H01L29/06 ,  H01L29/04 ,  H01L29/40

CPC分类号： H01L23/495 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L28/40 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0856 ,  H01L29/407 ,  H01L29/41 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7806 ,  H01L29/7809 ,  H01L29/781 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/37099

摘要： A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.

摘要翻译： 公开了半导体器件和方法。 一个实施例提供具有第一n型沟道FET和第二n型沟道FET的半导体管芯。 第一n型沟道FET的源极和第二n型沟道FET的漏极电耦合到第一侧的至少一个接触区域。 第一n型沟道FET的漏极，第一n型沟道FET的栅极，第二n型沟道FET的源极和第二n型沟道FET的栅极电耦合到接触区域 第二面。 第一n型沟道FET和第二n型沟道FET的接触区域彼此电分离。

公开(公告)号：US08889512B2

公开(公告)日：2014-11-18

申请号：US13281829

申请日：2011-10-26

申请人： Joachim Krumrey ,  Gerhard Noebauer ,  Martin Poelzl ,  Marc Probst

发明人： Joachim Krumrey ,  Gerhard Noebauer ,  Martin Poelzl ,  Marc Probst

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811

摘要： A transistor component and method of forming a transistor component. One embodiment provides a semiconductor arrangement including a semiconductor body having a at least one first trench, a first field electrode arranged in the lower trench section of the at least one first trench and being insulated from the semiconductor body by a field electrode dielectric. A dielectric layer is formed on the first field electrode in the at least one first trench, including depositing a dielectric material on a first side of the semiconductor body and on the field plate at a higher deposition rate than on sidewalls of the at least one first trench.

摘要翻译： 晶体管元件及形成晶体管元件的方法。 一个实施例提供一种半导体装置，其包括半导体本体，该半导体本体具有至少一个第一沟槽，第一场电极，布置在至少一个第一沟槽的下沟槽部分中，并且通过场电极电介质与半导体本体绝缘。 在所述至少一个第一沟槽中的所述第一场电极上形成电介质层，包括在所述半导体主体的第一侧和所述场板上以比所述至少一个第一沟槽的侧壁更高的沉积速率沉积介电材料 沟。

公开(公告)号：US08778751B2

公开(公告)日：2014-07-15

申请号：US13235550

申请日：2011-09-19

申请人： Martin Poelzl

发明人： Martin Poelzl

IPC分类号： H01L21/8238 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC分类号： H01L29/4236 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76286 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66681 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/78642

摘要： A semiconductor component includes a semiconductor body having a surface and a cutout in the semiconductor body. The cutout extends from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface. The cutout has a base and at least one sidewall. The component further includes a layer on the surface of the semiconductor body and in the cutout. The layer forms a well above the cutout. The well has a well base, a well edge and at least one well sidewall. The at least one well sidewall forms an angle α in the range of 20° to 80° with respect to the surface of the semiconductor body. The layer has at least one edge which, proceeding from the well edge, extends in the direction of the surface of the semiconductor body.

摘要翻译： 半导体部件包括在半导体本体中具有表面和切口的半导体本体。 切口从半导体本体的表面沿垂直于表面的方向延伸到半导体本体中。 切口具有基部和至少一个侧壁。 所述部件还包括在所述半导体主体的表面上和所述切口中的层。 该层在切口上方形成一个井。 井具有良好的基础，良好的边缘和至少一个井壁。 至少一个阱侧壁相对于半导体本体的表面形成在20°至80°的范围内的角度α。 该层具有至少一个边缘，其从阱边缘开始沿着半导体本体的表面的方向延伸。

公开(公告)号：US20120040505A1

公开(公告)日：2012-02-16

申请号：US13281829

申请日：2011-10-26

申请人： Joachim Krumrey ,  Gerhard Noebauer ,  Martin Poelzl ,  Marc Probst

发明人： Joachim Krumrey ,  Gerhard Noebauer ,  Martin Poelzl ,  Marc Probst

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811

摘要： A transistor component and method of forming a transistor component. One embodiment provides a semiconductor arrangement including a semiconductor body having a at least one first trench, a first field electrode arranged in the lower trench section of the at least one first trench and being insulated from the semiconductor body by a field electrode dielectric. A dielectric layer is formed on the first field electrode in the at least one first trench, including depositing a dielectric material on a first side of the semiconductor body and on the field plate at a higher deposition rate than on sidewalls of the at least one first trench.

摘要翻译： 晶体管元件及形成晶体管元件的方法。 一个实施例提供一种半导体装置，其包括半导体本体，该半导体本体具有至少一个第一沟槽，第一场电极，布置在至少一个第一沟槽的下沟槽部分中，并且通过场电极电介质与半导体本体绝缘。 在所述至少一个第一沟槽中的所述第一场电极上形成电介质层，包括在所述半导体主体的第一侧和所述场板上以比所述至少一个第一沟槽的侧壁更高的沉积速率沉积介电材料 沟。

公开(公告)号：US08093654B2

公开(公告)日：2012-01-10

申请号：US12834000

申请日：2010-07-11

申请人： Martin Poelzl ,  Walter Rieger

发明人： Martin Poelzl ,  Walter Rieger

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7805

摘要： A method for producing a vertical transistor component includes providing a semiconductor substrate, applying an auxiliary layer to the semiconductor substrate, and patterning the auxiliary layer for the purpose of producing at least one trench which extends as far as the semiconductor substrate and which has opposite sidewalls. The method further includes producing a monocrystalline semiconductor layer on at least one of the sidewalls of the trench, producing an electrode insulated from the monocrystalline semiconductor layer on the at least one sidewall of the trench and the semiconductor substrate.

摘要翻译： 一种用于制造垂直晶体管组件的方法包括：提供半导体衬底，向半导体衬底施加辅助层，以及对辅助层进行构图，以便制造至少一个延伸至半导体衬底并具有相对侧壁的沟槽 。 该方法还包括在沟槽的至少一个侧壁上制造单晶半导体层，产生与沟槽和半导体衬底的至少一个侧壁上的单晶半导体层绝缘的电极。

公开(公告)号：US07943955B2

公开(公告)日：2011-05-17

申请号：US12360263

申请日：2009-01-27

申请人： Oliver Haeberlen ,  Walter Rieger ,  Lutz Goergens ,  Martin Poelzl ,  Johannes Schoiswohl ,  Joachim Krumrey

发明人： Oliver Haeberlen ,  Walter Rieger ,  Lutz Goergens ,  Martin Poelzl ,  Johannes Schoiswohl ,  Joachim Krumrey

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/04 ,  H01L29/0856 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/781 ,  H01L29/7827 ,  H01L29/7835 ,  H01L2224/40245 ,  H01L2224/451 ,  H01L2224/48247 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides one semiconductor die with a first and a second FET. One of source/drain of the first FET and one of source/drain of the second FET are electrically coupled to at least one contact area at a first side of one semiconductor die, respectively. The other one of source/drain of the first FET, a gate of the first FET, the other one of source/drain of the second FET and the gate of the second FET are electrically coupled to contact areas at a second side of the one semiconductor die opposite to the first side, respectively. The contact areas of the other one of source/drain of the first FET, of the gate of the first FET, of the other one of source/drain of the second FET and of the gate of the second FET are electrically separated from each other, respectively.

摘要翻译： 一个方面是单片半导体开关和制造方法。 一个实施例提供具有第一和第二FET的一个半导体管芯。 第一FET的源极/漏极之一和第二FET的源极/漏极之一分别电耦合到一个半导体晶粒的第一侧上的至少一个接触区域。 第一FET的源极/漏极中的另一个，第一FET的栅极，第二FET的源极/漏极和第二FET的栅极中的另一个电耦合到第一FET的第二侧的接触区域 半导体管芯分别与第一侧相对。 第一FET的源极/漏极，第一FET的栅极，第二FET的源极/漏极和第二FET的栅极之间的另一个的接触区域彼此电分离 ， 分别。